JPS59201445A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the mismounting of a package to a chip surface by forming an identification pattern which indicates the type of the package in which an IC chip is contained on that IC chip. CONSTITUTION:An indication area 13 is provided to the pattern surface of an IC chip 11 and the type and terminal counts of a package in which the chip 11 is contained are indicated by a pattern in that area 13. For that purpose, when a mask, which allocates logic function units in a design circuit diagram to unit cells 12 of the chip 11, is formed, the identification pattern 15 is formed on the circumference zone of the chip 11. The pattern 15 is composed of the letters each of which has dimensions of 20-40mum. For instance, combination of English capital letters and small letters such as ''DIP 28'' indicates the ceramic DIP composition and terminal counts of 28. With this constitution, the type of the package corresponding to the IC chip 11 can be identified visually and the mismounting is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (3+ Technical Field of the Invention) The present invention relates to a semiconductor device having an identification pin on the surface of a semiconductor chip for indicating the type of semiconductor package and the number of bottles.

(bi) Background of the Technology One of the methods for forming large-scale integrated circuits (Ll) is the mass l slicing method in which a basic pattern is designed in advance and the connection method between the children is changed as necessary to form 11. In this method, a unit cell consisting of a resistor L1 transistor η, etc. is arranged in advance on a semiconductor element, the production process is the same up to the diffusion process with famous products, and only the wiring pattern is changed depending on the product. In order to achieve both the mass production effect of LSI and the multi-product nature of logic circuits, the back cages that house semiconductor devices are diversifying. Kate Ale, (I
Since the number of input/output terminals of C changes depending on the installation specifications, multiple types of packages are prepared with the number of terminals corresponding to Tl. Furthermore, as the types of packages themselves increase, the number of combinations of packages and devices on which devices are mounted has also increased.

IcI Prior Art and Problems FIG. 1 is a plan view showing an example of a pattern of a mass l-slice IC formed on a semiconductor integrated circuit chip, and FIG. 2 is a plan view of the semiconductor integrated circuit chip after wire bonding. In FIG. 1, a unit cell 2 consisting of a resistor, a transistor, etc. is formed in advance on a τ half-quadruple integrated circuit (y)1.

On the periphery of the semiconductor integrated circuit chip 1, there are 9 parts connected to the outside, ie power supply pads 3. It is configured by arranging a signal pad 4. The blocks in the circuit diagram are assigned to the unit cells 2 of the conductor integrated circuit chip 1 according to the design drawing, and the layout is further performed in the order of wiring processing between the blocks to provide a wiring pattern according to the configuration of the logic circuit. The patterned semiconductor integrated circuit block 1 is housed in a semiconductor package, and the pads and inner leads 5 on the package side are connected by wires 6 as shown in FIG. On the other hand, semiconductor integrated circuit chip 1
The number and arrangement of the signal pads on the top are fixed regardless of the circuit configuration of the IC, but the number of pads used among multiple pads varies depending on the circuit configuration of the IC, as shown in Figure 2. Therefore, multiple types of packages with corresponding number of bins are required. As described above, when there are a wide variety of combinations of semiconductor integrated circuit chips and packages that house them, it is impossible to distinguish the semiconductor integrated circuit chips from their appearance, and appropriate measures cannot be taken when assembling and mounting them, resulting in incorrect mounting.

Similarly, during testing, incorrect setup can cause damage to semiconductor devices.

td+ OBJECTS OF THE INVENTION In view of the above-mentioned points, it is an object of the present invention to prevent incorrect mounting by displaying the type of buff cage that accommodates a semiconductor integrated circuit chip on the surface of the chip.

According to the present invention, the structural purpose of the invention is achieved by forming on a semiconductor integrated circuit chip a functional pattern indicating the type of package in which the semiconductor integrated circuit chip is housed.

(fl　Embodiments of the invention An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a plan view showing a semiconductor integrated circuit chip in which the type and number of bins of a semiconductor package are displayed according to an embodiment of the present invention, and FIG. 4 is an enlarged view showing the display area of FIG. 3. In FIG. 3, a display area 13 is provided on the pattern surface of the semiconductor integrated circuit block 11, and the type and number of terminals (bin number) of the package that accommodates the semiconductor integrated circuit block 11 are displayed on the display area 13. It is displayed on the screen. As an example of a pattern display method, a logic function unit (program number) in a designed circuit diagram is assigned to 12t unit cells on a semiconductor chip, and a connection pattern is formed on a mask according to the configuration of the designed circuit. At the same time, the identification pattern 15 is formed and transferred to the display area 13 of the semiconductor integrated circuit chip 11 in the wiring formation process to form the identification pattern 15. For example, in the photoetching process, a mask having +15 pattern patterns and an aluminum film are formed, and then a photoresist film is formed. A photoresist film pattern is created by aligning the coated semiconductor substrate, overlapping exposure, and development, and using this as a mask, a desired aluminum pattern is transferred and formed by wet or dry etching. may be provided anywhere on the chip surface, but if it is provided at the four corners of the semiconductor integrated circuit chip 11 or in a blank space at one end, display can be performed without reducing the element formation area.The display process is as described above. A metal film (usually aluminum) is deposited on the substrate during patterning to form the final circuit configuration, and a circuit pattern and identification balloon are simultaneously formed using the photo-etching method described above), or a semiconductor integrated circuit. By performing this at the time of forming the pattern of the pad 14 provided around the 1000 tubes 11, it is possible to display without changing the production process.In addition, the identification pattern 15 has a thickness of 20μ for each character.
It is formed with a stroke of ~40μ, and for example, "DIP28" is a combination of English letters, lowercase letters, and C indicating the number of terminals, indicating a back cage with a ceramic dip structure that holds 28 bottles. Since the operator can visually recognize the type of package that corresponds to the semiconductor integrated circuit chip, incorrect mounting is prevented.Furthermore, since the display is minute and can be folded, it does not require a large space, so it is important to ensure that the display area is sufficient. The identification pattern may be formed by forming grooves on the surface of the semiconductor substrate in a process prior to wiring drawing, or a bar code or the like may be used as the pattern, and the assembly is performed by recognizing the bar code with a sensor. It is also easy to use C, which aims to automate the process.

Igl Effects of the Invention As explained in detail above, according to the present invention, by displaying the package type and number of terminals as the number on the surface of the conductor circuit, assembly and f:, f6 error can be avoided. The work efficiency is the same as above as it is possible to prevent the connection between PC and WA.

Moreover, it has great effects such as being able to display patterns in a normal process without reducing the mounting area.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of an identification pattern formed on a semiconductor integrated circuit board, FIG. 2 is a plan view of a semiconductor integrated circuit board after wire bonding, and FIG. 3 is an embodiment of the present invention. FIG. 4 is an enlarged view showing the display area of FIG. 3. FIG. In the figure 11... Semiconductor integrated circuit chip, 12...
... Unit cell, 13 ... Display area, 14.
...Pad, 15...Identification pattern.

Claims (1)

[Claims] 1. A semiconductor device, characterized in that a bell pattern indicating the type of package in which the semiconductor integrated circuit chip is housed is formed on the semiconductor integrated circuit chip.