JPS59202544A - 命令バツファ迂回装置 - Google Patents

命令バツファ迂回装置

Info

Publication number
JPS59202544A
JPS59202544A JP59005877A JP587784A JPS59202544A JP S59202544 A JPS59202544 A JP S59202544A JP 59005877 A JP59005877 A JP 59005877A JP 587784 A JP587784 A JP 587784A JP S59202544 A JPS59202544 A JP S59202544A
Authority
JP
Japan
Prior art keywords
instruction
register
instructions
execution
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59005877A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6240734B2 (2
Inventor
マーク・エドワード・バーガー
スチーブン・リー・ジヨージ
チヤツク・ホング・ナイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59202544A publication Critical patent/JPS59202544A/ja
Publication of JPS6240734B2 publication Critical patent/JPS6240734B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP59005877A 1983-05-02 1984-01-18 命令バツファ迂回装置 Granted JPS59202544A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US490813 1983-05-02
US06/490,813 US4635194A (en) 1983-05-02 1983-05-02 Instruction buffer bypass apparatus

Publications (2)

Publication Number Publication Date
JPS59202544A true JPS59202544A (ja) 1984-11-16
JPS6240734B2 JPS6240734B2 (2) 1987-08-29

Family

ID=23949573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59005877A Granted JPS59202544A (ja) 1983-05-02 1984-01-18 命令バツファ迂回装置

Country Status (4)

Country Link
US (1) US4635194A (2)
EP (1) EP0123922B1 (2)
JP (1) JPS59202544A (2)
DE (1) DE3485728D1 (2)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216032A (ja) * 1985-02-13 1986-09-25 Fujitsu Ltd 命令バツフア回路
JPS63106046A (ja) * 1986-10-22 1988-05-11 Mitsubishi Electric Corp デ−タ処理装置
US6754814B1 (en) 1998-12-17 2004-06-22 Fujitsu Limited Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions
JP2013527534A (ja) * 2010-05-24 2013-06-27 クアルコム，インコーポレイテッド 命令としてデータ値を評価するシステムおよび方法

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630075B2 (ja) * 1984-08-31 1994-04-20 株式会社日立製作所 キャッシュメモリを有するデータ処理装置
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
JPS62117001A (ja) * 1985-11-16 1987-05-28 Hitachi Ltd プログラマブルシ−ケンスコントロ−ラの入出力処理方法
DE3761278D1 (de) * 1986-04-23 1990-02-01 Siemens Ag Verfahren und anordnung zur beschleunigung der bereitstellung eines befehles im befehlsregister eines mikroprogrammgesteuerten prozessors.
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
EP0279953B1 (en) * 1987-02-24 1994-11-02 Texas Instruments Incorporated Computer system having mixed macrocode and microcode instruction execution
US5235686A (en) * 1987-02-24 1993-08-10 Texas Instruments Incorporated Computer system having mixed macrocode and microcode
US4882673A (en) * 1987-10-02 1989-11-21 Advanced Micro Devices, Inc. Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache
US5313601A (en) * 1988-01-30 1994-05-17 Nec Corporation Request control apparatus
JP2617974B2 (ja) * 1988-03-08 1997-06-11 富士通株式会社 データ処理装置
JP2564624B2 (ja) * 1988-09-20 1996-12-18 富士通株式会社 スタック方式
US4905141A (en) * 1988-10-25 1990-02-27 International Business Machines Corporation Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
JP2505887B2 (ja) * 1989-07-14 1996-06-12 富士通株式会社 命令処理システム
JP2710994B2 (ja) * 1989-08-29 1998-02-10 三菱電機株式会社 データ処理装置
JP2695017B2 (ja) * 1989-11-08 1997-12-24 富士通株式会社 データ転送方式
WO1991011765A1 (en) * 1990-01-29 1991-08-08 Teraplex, Inc. Architecture for minimal instruction set computing system
US5255371A (en) * 1990-04-02 1993-10-19 Unisys Corporation Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands
US6378061B1 (en) * 1990-12-20 2002-04-23 Intel Corporation Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit
JPH0695875A (ja) * 1991-01-09 1994-04-08 Mitsubishi Electric Corp マイクロコンピュータのメモリアクセス方法
US5655147A (en) * 1991-02-28 1997-08-05 Adaptec, Inc. SCSI host adapter integrated circuit utilizing a sequencer circuit to control at least one non-data SCSI phase without use of any processor
IL100127A0 (en) * 1991-03-11 1992-08-18 Future Domain Corp Scsi controller
JP2734465B2 (ja) * 1991-04-10 1998-03-30 三菱電機株式会社 ネットワーク用入出力装置
EP0547240B1 (en) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5659690A (en) * 1992-10-15 1997-08-19 Adaptec, Inc. Programmably configurable host adapter integrated circuit including a RISC processor
US5463748A (en) * 1993-06-30 1995-10-31 Intel Corporation Instruction buffer for aligning instruction sets using boundary detection
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
JP2924643B2 (ja) * 1994-05-19 1999-07-26 ヤマハ株式会社 ディジタル信号処理方法及び装置
US5682480A (en) * 1994-08-15 1997-10-28 Hitachi, Ltd. Parallel computer system for performing barrier synchronization by transferring the synchronization packet through a path which bypasses the packet buffer in response to an interrupt
US5729719A (en) * 1994-09-07 1998-03-17 Adaptec, Inc. Synchronization circuit for clocked signals of similar frequencies
JP3569811B2 (ja) * 1995-01-25 2004-09-29 株式会社ルネサステクノロジ パイプライン処理機能を有するデータ処理装置
US5754806A (en) * 1995-11-03 1998-05-19 Holtek Microelectronics, Inc. Memory table look-up device and method
US5928355A (en) * 1997-06-27 1999-07-27 Sun Microsystems Incorporated Apparatus for reducing instruction issue stage stalls through use of a staging register
US5918034A (en) * 1997-06-27 1999-06-29 Sun Microsystems, Inc. Method for decoupling pipeline stages
US20040111594A1 (en) * 2002-12-05 2004-06-10 International Business Machines Corporation Multithreading recycle and dispatch mechanism
US9354887B2 (en) * 2010-06-28 2016-05-31 International Business Machines Corporation Instruction buffer bypass of target instruction in response to partial flush
JP6155723B2 (ja) * 2013-03-18 2017-07-05 富士通株式会社 レーダ装置及びプログラム
JP7373413B2 (ja) 2020-01-21 2023-11-02 大王製紙株式会社 シート集合包装体の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729154A (en) * 1980-07-29 1982-02-17 Fujitsu Ltd Instruction buffer controlling system
JPS5843042A (ja) * 1981-09-08 1983-03-12 Fujitsu Ltd 先行制御方式

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2226079A5 (2) * 1973-04-13 1974-11-08 Honeywell Bull Soc Ind
US4040031A (en) * 1973-04-13 1977-08-02 Compagnie Honeywell Bull (Societe Anonyme) Computer instruction control apparatus and method
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4156906A (en) * 1977-11-22 1979-05-29 Honeywell Information Systems Inc. Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4268907A (en) * 1979-01-22 1981-05-19 Honeywell Information Systems Inc. Cache unit bypass apparatus
US4500954A (en) * 1981-10-15 1985-02-19 International Business Machines Corporation Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729154A (en) * 1980-07-29 1982-02-17 Fujitsu Ltd Instruction buffer controlling system
JPS5843042A (ja) * 1981-09-08 1983-03-12 Fujitsu Ltd 先行制御方式

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216032A (ja) * 1985-02-13 1986-09-25 Fujitsu Ltd 命令バツフア回路
JPS63106046A (ja) * 1986-10-22 1988-05-11 Mitsubishi Electric Corp デ−タ処理装置
US6754814B1 (en) 1998-12-17 2004-06-22 Fujitsu Limited Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions
JP2013527534A (ja) * 2010-05-24 2013-06-27 クアルコム，インコーポレイテッド 命令としてデータ値を評価するシステムおよび方法
JP2015133129A (ja) * 2010-05-24 2015-07-23 クアルコム，インコーポレイテッド 命令としてデータ値を評価するシステムおよび方法
US9361109B2 (en) 2010-05-24 2016-06-07 Qualcomm Incorporated System and method to evaluate a data value as an instruction

Also Published As

Publication number Publication date
EP0123922B1 (en) 1992-05-20
EP0123922A3 (en) 1987-07-29
US4635194A (en) 1987-01-06
DE3485728D1 (de) 1992-06-25
JPS6240734B2 (2) 1987-08-29
EP0123922A2 (en) 1984-11-07

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