JPS59208755A - 半導体装置のパツケ−ジ及びその製造方法 - Google Patents

半導体装置のパツケ−ジ及びその製造方法

Info

Publication number
JPS59208755A
JPS59208755A JP58083187A JP8318783A JPS59208755A JP S59208755 A JPS59208755 A JP S59208755A JP 58083187 A JP58083187 A JP 58083187A JP 8318783 A JP8318783 A JP 8318783A JP S59208755 A JPS59208755 A JP S59208755A
Authority
JP
Japan
Prior art keywords
semiconductor device
external electrode
package
resin
mold layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58083187A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0473297B2 (2
Inventor
Katsuhiko Akiyama
秋山　克彦
Yuji Kajiyama
梶山　雄次
Tetsuo Ono
小野　鉄雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP58083187A priority Critical patent/JPS59208755A/ja
Publication of JPS59208755A publication Critical patent/JPS59208755A/ja
Publication of JPH0473297B2 publication Critical patent/JPH0473297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58083187A 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法 Granted JPS59208755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58083187A JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Publications (2)

Publication Number Publication Date
JPS59208755A true JPS59208755A (ja) 1984-11-27
JPH0473297B2 JPH0473297B2 (2) 1992-11-20

Family

ID=13795315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58083187A Granted JPS59208755A (ja) 1983-05-12 1983-05-12 半導体装置のパツケ−ジ及びその製造方法

Country Status (1)

Country Link
JP (1) JPS59208755A (2)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131449U (2) * 1986-02-13 1987-08-19
JPS62131656U (2) * 1986-02-14 1987-08-19
JPS63301531A (ja) * 1987-06-01 1988-12-08 Nec Corp 混成集積回路装置
JPH08148603A (ja) * 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
JPH09134982A (ja) * 1995-11-08 1997-05-20 Fujitsu Ltd 半導体装置及びその製造方法
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
DE10063041A1 (de) * 2000-12-18 2002-07-04 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltung
EP0794572A3 (en) * 1996-03-07 2003-09-03 Matsushita Electric Industrial Co., Ltd. Electronic component, method for making the same, and lead frame and mold assembly for use therein
US7189599B2 (en) * 2001-05-30 2007-03-13 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131449U (2) * 1986-02-13 1987-08-19
JPS62131656U (2) * 1986-02-14 1987-08-19
JPS63301531A (ja) * 1987-06-01 1988-12-08 Nec Corp 混成集積回路装置
JPH08148603A (ja) * 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
JPH09134982A (ja) * 1995-11-08 1997-05-20 Fujitsu Ltd 半導体装置及びその製造方法
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
EP0794572A3 (en) * 1996-03-07 2003-09-03 Matsushita Electric Industrial Co., Ltd. Electronic component, method for making the same, and lead frame and mold assembly for use therein
DE10063041A1 (de) * 2000-12-18 2002-07-04 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltung
US6649450B2 (en) 2000-12-18 2003-11-18 Infineon Technologies Ag Method of producing an integrated circuit and an integrated circuit
DE10063041B4 (de) * 2000-12-18 2012-12-06 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Leadless-Gehäuse-Schaltung und integrierte Leadless-Gehäuse-Schaltung
US7189599B2 (en) * 2001-05-30 2007-03-13 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device

Also Published As

Publication number Publication date
JPH0473297B2 (2) 1992-11-20

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