JPS5927543A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5927543A
JPS5927543A JP57137705A JP13770582A JPS5927543A JP S5927543 A JPS5927543 A JP S5927543A JP 57137705 A JP57137705 A JP 57137705A JP 13770582 A JP13770582 A JP 13770582A JP S5927543 A JPS5927543 A JP S5927543A
Authority
JP
Japan
Prior art keywords
film
individual element
element isolation
silicon oxide
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57137705A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6242382B2 (2
Inventor
Moriyoshi Nakajima
盛義 中島
Akira Ando
安東　亮
Hirokazu Miyoshi
三好　寛和
Akira Nishimoto
西本　章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57137705A priority Critical patent/JPS5927543A/ja
Publication of JPS5927543A publication Critical patent/JPS5927543A/ja
Publication of JPS6242382B2 publication Critical patent/JPS6242382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP57137705A 1982-08-06 1982-08-06 半導体装置の製造方法 Granted JPS5927543A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57137705A JPS5927543A (ja) 1982-08-06 1982-08-06 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57137705A JPS5927543A (ja) 1982-08-06 1982-08-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5927543A true JPS5927543A (ja) 1984-02-14
JPS6242382B2 JPS6242382B2 (2) 1987-09-08

Family

ID=15204888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57137705A Granted JPS5927543A (ja) 1982-08-06 1982-08-06 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5927543A (2)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622737A (en) * 1984-09-25 1986-11-18 Sgs-Ates Componeti Electtronici S.P.A. Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell
US4758530A (en) * 1986-12-08 1988-07-19 Delco Electronics Corporation Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers
JPH0172728U (2) * 1987-11-04 1989-05-16
JPH01143352A (ja) * 1987-11-30 1989-06-05 Nec Kyushu Ltd 溝容量部を備えた半導体記憶装置
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US5128274A (en) * 1989-08-01 1992-07-07 Matsushita Electric Industrial Co., Ltd. Method for producing a semiconductor device having a LOCOS insulating film with at least two different thickness
US5498564A (en) * 1994-08-03 1996-03-12 International Business Machines Corporation Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction
US5679600A (en) * 1995-10-11 1997-10-21 Micron Technology, Inc. Double locos for submicron isolation

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622737A (en) * 1984-09-25 1986-11-18 Sgs-Ates Componeti Electtronici S.P.A. Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US4758530A (en) * 1986-12-08 1988-07-19 Delco Electronics Corporation Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers
JPH0172728U (2) * 1987-11-04 1989-05-16
JPH01143352A (ja) * 1987-11-30 1989-06-05 Nec Kyushu Ltd 溝容量部を備えた半導体記憶装置
US5128274A (en) * 1989-08-01 1992-07-07 Matsushita Electric Industrial Co., Ltd. Method for producing a semiconductor device having a LOCOS insulating film with at least two different thickness
US5498564A (en) * 1994-08-03 1996-03-12 International Business Machines Corporation Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction
US5679600A (en) * 1995-10-11 1997-10-21 Micron Technology, Inc. Double locos for submicron isolation

Also Published As

Publication number Publication date
JPS6242382B2 (2) 1987-09-08

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