JPS5934641A - Measuring method for characteristic of semiconductor element - Google Patents
Measuring method for characteristic of semiconductor elementInfo
- Publication number
- JPS5934641A JPS5934641A JP57145335A JP14533582A JPS5934641A JP S5934641 A JPS5934641 A JP S5934641A JP 57145335 A JP57145335 A JP 57145335A JP 14533582 A JP14533582 A JP 14533582A JP S5934641 A JPS5934641 A JP S5934641A
- Authority
- JP
- Japan
- Prior art keywords
- probe card
- probe
- wafers
- stage
- stages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
この発明は半導体ウェーハに整列して形成された多数の
半導体素子を個々に特性測定する方法で、詳しくはプロ
ーブカードから突設されたプローブニードルに可動ステ
ージ上に保持された半導体ウェーハの半導体素子を1つ
ずつ電気的接触させる方式の特性測定方法の改良に関す
るO
背景技術
通常、トランジスタやICなどの半導体素子の特性測定
は1枚の半導体ウェーハに複数個が一括して形成された
段階で行われている。この種の半導体素子特性測定は1
つの半導体素子の表面電極群に当接するパターンのプロ
ーブニードル群を有するプローブカードを用いて行う方
式か一般的で、その従来例を第1図及び第2図の具体的
装置でもって説明する。[Detailed Description of the Invention] Technical Field This invention relates to a method for individually measuring the characteristics of a large number of semiconductor elements formed in alignment on a semiconductor wafer. O Concerning improvement of a method for measuring characteristics by electrically contacting semiconductor elements of a held semiconductor wafer one by one Background technology Normally, characteristics of semiconductor elements such as transistors and ICs are measured by measuring a plurality of semiconductor elements on one semiconductor wafer at once. This is done at the stage when it is formed. This type of semiconductor device characteristic measurement is 1
A common method is to use a probe card having a group of probe needles in a pattern that comes into contact with a group of surface electrodes of one semiconductor element, and a conventional example thereof will be explained using a specific device shown in FIGS. 1 and 2.
第1図及び第2図において、(1)は半導体ウェーハ(
以下単にウェーハと称す) 、(2)はウェーハ(1)
に行・列状の配列で形成された複数の半導体素子(以下
単に素子と称す)、(3)はウエーハ(1)を上面で水
平に保持する可動式ステージ、(4)はステージ(3)
を水平なX1Y方向と垂直な2方向の上下に適宜間歇移
動させるステージ駆動制御部である。(5)はステージ
(3)の上方定位置に固定配置された水平なプローブカ
ード、(6)はプローブカード(5)を支持して外部の
特性測定回路を組込んだテスター(ア)に電気的配線す
るソケットである。プローブカード(5)は中央部に1
つの窓孔(8)を有し、この窓孔(8)の周縁から中央
部下方に向けて複数本のプローブニードルからなるプロ
ーブニードル群(9)が突設される。1つ1つのプロー
ブニードルは先端が1つの半導体素子(2)の表面電極
の1つ1つに当接するパターンで形成すれ、各プローブ
ニードルはプローブカード(5)とソケット(6)を介
してテスター(7)に配線される。In Figures 1 and 2, (1) is a semiconductor wafer (
(hereinafter simply referred to as wafer), (2) is wafer (1)
(3) is a movable stage that holds the wafer (1) horizontally on its upper surface; (4) is the stage (3);
This is a stage drive control unit that moves the stage intermittently up and down in two directions, horizontal X1Y directions and perpendicular directions. (5) is a horizontal probe card fixedly placed above the stage (3), and (6) is a tester (A) that supports the probe card (5) and incorporates an external characteristic measurement circuit. It is a socket for wiring. The probe card (5) is 1 in the center.
A probe needle group (9) consisting of a plurality of probe needles is provided protruding from the periphery of the window hole (8) toward the center downward. Each probe needle is formed in a pattern in which the tip contacts each surface electrode of one semiconductor element (2), and each probe needle is connected to a tester through a probe card (5) and a socket (6). (7) is wired.
上記装置による特性測定動作は先ず、ステージ(3)上
のウェーハ(1)をプローブカード(5)に対して目合
せず葛。次にステージ(3)をX、Y、Z方向に間歇移
動させてウェーハ(1)での素子(2)を1つずつプロ
ーブカード(5)の中央の測定ポジションへ順次に送り
込み、測定ポジションで順次に素子(2)の表面電極群
をプローブニードル群(9)に接触させてテスター(7
)でもって特性測定を行う。1つの素子(2)の特性測
定結果が良と出ると次の素子(2)の測定動作へ連続し
て移行し、特性測定結果が不良と出ると不良素子表面に
不良識別マークを形成させる。この不良識別マークを形
成する手段には不良素子表面にインクを塗布するマーキ
ングペンや、引掻き傷を付けるビンなどが用いられ、こ
れらペンやビンはプローブカード(5)の窓孔(8)上
方に待機し、不良素子がくると下降して不良識別マーク
を付ける動作をする。このような不良識別マークは後工
程で素子(2)を良品と不良品に選別する時に利用され
る。また不良素子に不良識別マークを付ける代りに不良
素子のウェーハ(1)に対する位tWをマイクロコンピ
ュータに記憶させて、この記憶内容に基づいて後の選別
処理を行うことも最近は実行されている。In the characteristic measurement operation using the above device, first, the wafer (1) on the stage (3) is not aligned with the probe card (5). Next, the stage (3) is moved intermittently in the X, Y, and Z directions to sequentially feed the elements (2) on the wafer (1) one by one to the measurement position in the center of the probe card (5). Sequentially, the surface electrode group of the element (2) is brought into contact with the probe needle group (9) and the tester (7
) to measure the characteristics. When the characteristic measurement result of one element (2) is found to be good, the measurement operation of the next element (2) is successively carried out, and when the characteristic measurement result is found to be poor, a defect identification mark is formed on the surface of the defective element. A marking pen that applies ink to the surface of the defective element or a bottle that scratches the surface of the defective element is used as a means for forming this defective identification mark, and these pens and bottles are placed above the window hole (8) of the probe card (5). It waits, and when a defective element arrives, it descends and attaches a defect identification mark. Such a defective identification mark is used in a subsequent process to classify the elements (2) into good and defective products. Furthermore, instead of attaching a defective identification mark to a defective element, it has recently been practiced to store the value tW for the wafer (1) of the defective element in a microcomputer, and to perform subsequent selection processing based on this stored content.
ところで、テスター(7)が1つの素子(2)を特性測
定するに要する測定時間をTとすると、上記装置は第6
図に示すタイムチャートの如く11作を繰返す。即ち、
1つの素子(2)の測定完了後ステージ(3)が定ピツ
チ下降し、横に定ピツチ移動し、そして定ピツチ上昇し
て次の素子(2)の測定が開始される。このステージ移
動の間のテスター(7)は動作せずに待機し、この待ち
時間Wは約0.3〜0.5秒程度必要とされ、これがた
め1枚のウェーハ(1)の素子(2)の全ての特性測定
を完了するまでに長時間を要し、インデックス改善が難
しかった。By the way, if the measurement time required for the tester (7) to measure the characteristics of one element (2) is T, then the above device
The 11 works are repeated as shown in the time chart shown in the figure. That is,
After the measurement of one element (2) is completed, the stage (3) is lowered by a fixed pitch, moved laterally by a fixed pitch, and then raised by a fixed pitch to start measuring the next element (2). During this stage movement, the tester (7) does not operate and waits, and this waiting time W is about 0.3 to 0.5 seconds. ) It took a long time to complete all characteristic measurements, making it difficult to improve the index.
このような測定時間の無駄を少なくする方式として、上
記同様なステージとプローブカードの組を2組並設し、
2つのプローブカードを1つのテスターに配線しておい
て、一方の組で1枚のウェーハの素子の特性測定を行っ
ている間に他の組でステージ移動を行うものがある。こ
の方式によると共用されるテスターはほぼ連続的に動作
して待ち時間が大幅に短縮されるが、2台のステージを
並設するため全体の設置床面積が甚大となること、2台
のステージ上のウェーハとプローブカードとの目合せに
大変手間取って全体の作業時間の短縮化にあまり効を奏
さないことなどの問題があった。As a method to reduce such wasted measurement time, two sets of stages and probe cards similar to those described above are installed in parallel.
There is a tester in which two probe cards are wired to one tester, and one set measures the characteristics of elements on one wafer while the other set moves the stage. According to this method, the shared tester operates almost continuously and the waiting time is greatly reduced, but since the two stages are installed side by side, the total installation floor space becomes extremely large, and the two stages There is a problem in that it takes a lot of time to align the upper wafer and the probe card, and it is not very effective in shortening the overall working time.
また水平なステージ上方にプローブカードを設置するも
ので、不良素子表面に不良り別マークを付すものである
と、不良素子表面へのマーキング時にインクや引掻き傷
による屑が不良素子周辺に並ぶ素子へと飛散して落下付
着し、その素子が良品であっても不良品とする不都合が
あり、改善策が要望されていた。In addition, if a probe card is installed above a horizontal stage and a mark is placed on the surface of a defective element to identify the defect, ink and scratches may be deposited on the elements surrounding the defective element when marking the surface of the defective element. There is a problem in that the element scatters, falls and adheres to the element, and even if the element is a good one, it becomes a defective one.Therefore, there has been a demand for an improvement measure.
発明の開示
本発明はかかる従来の各問題点に鑑みてなされたもので
、1枚のプローブカードの両面にプローブニードル群を
突設して2枚のウェーハの素子の特性測定を交互に行う
ようにした半導体素子特性測定方法を提供する。DISCLOSURE OF THE INVENTION The present invention has been made in view of these conventional problems, and includes a probe card in which groups of probe needles are provided protruding from both sides of one probe card to alternately measure characteristics of elements on two wafers. A method for measuring semiconductor device characteristics is provided.
本発明は両面にプローブニードル群を有するプローブカ
ードと、このプローブカードの両面に平行に対向させて
計2枚のウェーハを保持する計2台のステージの王者を
平行及び垂直方向に相対的に間歇移動させることで実行
される。The present invention provides a probe card having a group of probe needles on both sides, and a total of two stage champions that hold a total of two wafers facing each other in parallel to both sides of the probe card, and relatively intermittently in the parallel and perpendicular directions. This is done by moving.
プローブカードの2つのプローブニードル群は1つのテ
スターに配線され、2台のステージの一方は他方のステ
ージのウェーハの素子が1つのプローブニードル群に接
触して特性測定をされている間に位置移動し、これによ
りテスターの待ち時間が短縮化されてインデックスが大
幅に向上する。上記王者の最も有効な配置は三者共に鉛
直な縦配置であるが、水平な横配置であってもインデッ
クス的な効果には変りない。The two groups of probe needles on the probe card are wired to one tester, and one of the two stages moves while the elements of the wafer on the other stage are in contact with one group of probe needles to measure their characteristics. However, this reduces wait time for testers and significantly improves the index. The most effective arrangement for the above-mentioned king is a vertical arrangement in which all three are arranged vertically, but even if they are arranged horizontally horizontally, the index-like effect will not change.
発明を実施するための最良の形態
上記王者を縦配置した本発明の具体的実施装置例を第4
図に示すと、00)は鉛直方向に固定前)丘された1つ
のプローブカード、(U)及び(ロ)はプローブカード
(10)の両面に突設した2つの第1、第2プローブニ
ードル群、03)は第1、第2プローブニードル群(l
υμs)を配線する1つのテスターである。H及びα5
)はプローブカードαりの両側に平行に配置された2台
の可動酸第1、第2ステージで、各々の内面に1枚ずつ
ウェーハ(16) (1°?)が真空吸着等の手段で保
持され、各ウェーハ(16バx7)はプローブカードα
0)の両面に平行に対向する。BEST MODE FOR CARRYING OUT THE INVENTION A specific example of an apparatus for implementing the present invention in which the above-mentioned kings are vertically arranged is shown in the fourth example.
As shown in the figure, 00) is one probe card that is tilted vertically (before being fixed), and (U) and (B) are two first and second probe needles protruding from both sides of the probe card (10). Group, 03) is the first and second probe needle group (l
This is one tester for wiring υμs). H and α5
) are two movable acid first and second stages arranged parallel to each other on both sides of the probe card, and one wafer (16) (1°?) is attached to each inner surface by means such as vacuum suction. Each wafer (16 bars x 7) is held by a probe card α
0) parallel to both sides.
(18)及び(19)は各ステージa→(15)を独立
して鉛直方向及びプローブカード00)と直交する水平
方向の上下左右方向に間歇送りして各々のウェーハ(1
6) (17)の各素子1120) (21)を対応す
る各プローブニードル群(11) (+2)に接触する
測定ポジションに順次に送り込むステージ駆動制御部で
ある。In (18) and (19), each stage a → (15) is independently intermittently fed in the vertical direction and in the horizontal direction perpendicular to the probe card 00), and each wafer (1
6) A stage drive control unit that sequentially sends each element 1120) (21) of (17) to a measurement position in contact with each corresponding probe needle group (11) (+2).
この第4図装置は第5図のタイムチャートの要領で測定
動作を行う。先ず第1、第2ステージθ慢(15)にウ
ェーハ(16) (17)をセットし、ウェーハ(16
)(17)をプローブカードα印に対して目合せする。The apparatus shown in FIG. 4 performs measurement operations in accordance with the time chart shown in FIG. First, set the wafers (16) (17) on the first and second stages θ (15), and
) (17) to the probe card α mark.
この目合せは両ウェーハ(16)α7)がプローブカー
ドθ0)の両面に対向しているので同時且つ容易に行え
る。測定動作は例えば先ず第1ステージ0→をプローブ
カード00)の方向に定ピッチ送りしてウェー八06ノ
の1つの素子に)の表面電極群を第1ブローフニードル
群(11)に接触させてこの素子(財)の特性測定を行
う。測定が完了して第1ステージ04)をプローブカー
ド(1(itから離すと同時に第2ステージ05)をプ
ローブカード(lO)の方向に定ピッチ送りして別のウ
ェーハα7)の1つの素子参りを、第2プローブニード
ル群(ロ)に接触させて特性測定を行う。この測定時間
の間に第1ステージ(14)を次の素子し0)が第1プ
ローブニードル(11)と対向する位置まで移行させて
待機させておく。第2プローブニードル(ロ)による素
子暢υの特性測定が完了して第2ステージ(15)がプ
ローブカード(]0)から離れる時点で第1ステージ0
4)を再度プローブカード(JO)に近付けて2個目の
素子しO)の特性測定を行い、この間第2ステージ(1
5)を次の素子娑υが第2プローブニードル群(ロ)に
対向する位1θまで移行させて待機させておく。以後上
記動作を繰り返し、第1、第2プローブニードル0υ(
財)で交互に素子に)及び0υの特注測定ン行うつこの
ようにするとテスター(13)は待ち時間無く連続して
素子の髄性測定を行い、作業能率が最大となる。This alignment can be performed simultaneously and easily since both wafers (16) α7) face both sides of the probe card θ0). In the measurement operation, for example, first, the first stage 0 → is sent at a fixed pitch in the direction of the probe card 00), and the surface electrode group of one element of the wafer 806 is brought into contact with the first blow needle group (11). Measure the characteristics of the lever element (goods). After the measurement is completed, the first stage 04) is separated from the probe card (1 (IT), and at the same time the second stage 05) is sent at a fixed pitch in the direction of the probe card (lO) to move to one element of another wafer α7). is brought into contact with the second probe needle group (b) to measure the characteristics. During this measurement time, the first stage (14) is moved to a position where the next element 0) faces the first probe needle (11) and is kept on standby. At the point when the second stage (15) leaves the probe card (]0) after the characteristic measurement of the element current υ by the second probe needle (b) is completed, the first stage 0
4) is brought close to the probe card (JO) again to measure the characteristics of the second element O), and during this time the second stage (1
5) is moved to a position 1θ where the next element υ faces the second probe needle group (b) and is kept on standby. After that, repeat the above operation until the first and second probe needles are 0υ(
By doing so, the tester (13) can perform the medullary measurements of the element continuously without waiting time, and the work efficiency is maximized.
上記動作で測定結果が不良と出た素子に対し、その素子
表面に不良順別マークを付す場合を考える。この時、イ
ンクや引掻き傷によるマーキング動作でインクや引掻き
傷による屑が飛ぶが、これはウェーハが鉛直配置のため
ウェーハ上に落下することなく排除されるので不良素子
周辺の良品素子は安全である坏良降別マークをマーキン
グするペンやビン等のマーカはプローブカードの板厚を
大きくしてその中に収納させればよい。また不良識別マ
ークを不良素子に付ス代りに不良菓子の位置をマイクロ
コンピュータに記憶させる場合はプローブカードを十分
に薄くすればよい。Let us consider a case where a mark is attached to the surface of an element whose measurement result is found to be defective in the above operation, indicating the order of failure. At this time, the ink and scratches fly away due to the marking operation, but since the wafer is arranged vertically, this is removed without falling onto the wafer, so the good devices around the defective devices are safe. A marker such as a pen or a bottle for marking the farewell mark may be housed in a thicker probe card. Furthermore, if the location of a defective confectionery is to be stored in a microcomputer instead of attaching a defective identification mark to a defective element, the probe card may be made sufficiently thin.
上記縦配置構造にすると1つのプローブニードル・2台
のステージの設置床面積が小さくでき、また重量の比較
的大きいステージの水平方向の移動制御が容易にできる
が、本発明はこの縦配置例に限らず、第4図のプローブ
カード00)、各ステージ0荀05)を水平にした横置
配置の構造にすることも町¥Jbである。The above-mentioned vertical arrangement structure allows the installation floor area of one probe needle and two stages to be reduced, and also makes it easy to control the horizontal movement of the comparatively heavy stage. However, it is also possible to arrange the probe card 00) and each stage 05) horizontally in a horizontal arrangement as shown in FIG.
また本発明は2台のステージを固定式或いは半固定式に
してプローブカード側を2つのステージ間に往復動させ
る構造にしても実行は可能である。Further, the present invention can be implemented by using a structure in which two stages are fixed or semi-fixed and the probe card side is moved back and forth between the two stages.
以上のように本発明によればプローブカードの両m1の
プローブニードル群が待ち時間無く交互に素子の特性測
定を行・5ので、特性測定装置の大幅な稼動率向上が図
れ、インデックス改善が実現できる。またプローブカー
ドや各ステージを鉛直配置することがiJ能で、このよ
う(こすることにより装置全体の床面積の縮小化が図れ
、またマーキング屑のウェーハ上への落下付着防止が図
れて歩留りか向上する。As described above, according to the present invention, the probe needle groups of both m1 of the probe card measure the characteristics of the element alternately without waiting time.5, so the operating rate of the characteristic measuring device can be greatly improved, and the index can be improved. can. In addition, it is possible to arrange the probe card and each stage vertically, which reduces the floor space of the entire equipment and also improves yield by preventing marking debris from falling onto the wafer. improves.
第1図及び第2図は従来方法による牛導体素子特性測定
装置の一例を示す要部平面図及び側面図、第6図は第1
図の装置の動作タイムチャート、第4図は本発明の方法
の具体的実施装置例を示す要部側面図、第5図は第4図
の装置の動作タイムチャートである。
00)・・・プローブカード、(1υ、(12)・・・
プローブニードル群、O勾・・・第1ステージ、(ロ)
)・・・第2ステージ、’(i6) 、(17)・・・
半導体ウェーハ、−1@υ・・・半導体素子。
G(図
鼾2図
憔3v
4 1d
l)Figures 1 and 2 are a plan view and a side view of essential parts showing an example of a conventional method for measuring the characteristics of a cattle conductor element, and Figure 6 is a
FIG. 4 is a side view of a main part showing a specific example of an apparatus for carrying out the method of the present invention, and FIG. 5 is an operation time chart of the apparatus shown in FIG. 00)...Probe card, (1υ, (12)...
Probe needle group, O slope... 1st stage, (b)
)...2nd stage, '(i6), (17)...
Semiconductor wafer, -1@υ...semiconductor element. G (Figure snoring 2 Figure 3v 4 1d l)
Claims (1)
素子を個々に特性測定する方法であって、半導体素子の
表面電極に当接するノぐターンのプローブニードル群を
両面に突設した1つのプローブカードと、プローブカー
ドの両面Gこ対向させて半導体ウェーハを保持する2つ
の第1、第2ステージを配置し、プローブカードを第1
、第2ステージ間を間歇的に往後移動させて、プローブ
カード両面の各プローブニードル群に第1、第2ステー
ジの各半導体ウエーノ・を交互に近接させて第1、第2
ステージの半導体ウエーノ1における半導体素子の特性
測定を連続して行うようにしたことを特徴とする半導体
素子特性測定方法。(1) A method for individually measuring the characteristics of a plurality of semiconductor elements formed on a semiconductor wafer 71, in which a single probe card is provided with a group of nog-turn probe needles protruding from both sides that come into contact with the surface electrodes of the semiconductor elements. Then, two first and second stages that hold semiconductor wafers are arranged so that both sides of the probe card face each other, and the probe card is placed on the first stage.
, the semiconductor wafers of the first and second stages are alternately moved close to each probe needle group on both sides of the probe card by intermittently moving back and forth between the second stages.
A method for measuring characteristics of a semiconductor device, characterized in that characteristics of a semiconductor device on a semiconductor wafer 1 of a stage are continuously measured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145335A JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145335A JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5934641A true JPS5934641A (en) | 1984-02-25 |
| JPH038584B2 JPH038584B2 (en) | 1991-02-06 |
Family
ID=15382787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145335A Granted JPS5934641A (en) | 1982-08-20 | 1982-08-20 | Measuring method for characteristic of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5934641A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61234543A (en) * | 1985-04-11 | 1986-10-18 | Nippon Maikuronikusu:Kk | Semiconductor wafer prober |
| JPH01157543A (en) * | 1988-11-17 | 1989-06-20 | Tokyo Electron Ltd | Wafer prober |
-
1982
- 1982-08-20 JP JP57145335A patent/JPS5934641A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61234543A (en) * | 1985-04-11 | 1986-10-18 | Nippon Maikuronikusu:Kk | Semiconductor wafer prober |
| JPH01157543A (en) * | 1988-11-17 | 1989-06-20 | Tokyo Electron Ltd | Wafer prober |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH038584B2 (en) | 1991-02-06 |
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