JPS593677A - Parallel synchronous operation control method - Google Patents

Abstract

PURPOSE:To secure synchronism, by dividing the frequency of a clock signal through plural microprocessors, comparing one of frequency-divided signal as a reference signal with others, and inhibiting clock input for signals with differences and making corrections. CONSTITUTION:A clock signal CK from an oscillator 3 is inputted to the normal and reverse input terminals of a main processor 1, which outputs a main frequency-divided signal Cm. When frequency-division outputs Cs and Cm of a slave processor 2 are both at a level ''0'', the output Ga of an ENR5 is at a level ''1'' and an FF6 latches it; when the signal CK rises, the FF6 is triggered and an AND gate 7 generates an output. A positive and a negative signal CK are inputted to the slave processor 2, which starts outputting a subordinate frequency- divided signal Cs; and the outputs Cm and Cs are out of phase with each other and the output Ga goes down to the level ''0'' to cut off the signals to the processor 2, so that the Cs is at the level ''0'' continuously. When the CK goes down to ''0'', the ENR5 generates the output again and the gate 7 outputs ''1''. At this time, the Cm and Cs are put in phase at the timing of the CK. Thus, the synchronism is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention divides the frequency of an input clock signal using a built-in frequency divider circuit to form a frequency divided signal for controlling operation timing. The present invention relates to a parallel synchronous operation control method that attempts to match the phases of frequency-divided signals of each microprocessor using a simple method using a clock signal.

Conventionally, microprocessors (hereinafter referred to as processors)
As they have been integrated into integrated circuits, they have improved functionality and processing speed, but they do not have a full-fledged fault diagnosis function like that of large computers, so they are not suitable for devices using processors. When high reliability is required, important circuit parts are
Is it necessary to configure a parallel redundant system such as out of M) to detect and process failures?

In order to construct the above-mentioned parallel redundant system, it is necessary to provide a plurality of processors in parallel and to perform parallel synchronous operations by synchronizing machine cycles.

However, when using multiple microprocessors such as Intel's 8085A processor, each of which has a built-in frequency divider circuit that divides the input clock signal to form a frequency-divided signal for controlling operation timing, Even if the same clock signal is input to each processor, the phases of the divided signals of each processor do not match, making it impossible to synchronize the machine cycles and making parallel synchronous operation impossible. becomes impossible.

This invention was made with the above points in mind,
In a parallel synchronous operation control method for operating a plurality of microprocessors in parallel and synchronously, dividing an input clock signal by a built-in frequency dividing circuit to form a divided signal for controlling operation timing, a predetermined microprocessor is always In addition to inputting the clock signal, a reference frequency division signal consisting of the frequency division signal of the predetermined microprocessor and a sub-frequency division signal consisting of the frequency division signal of each of the other microprocessors are input, respectively. When the logic level of the reference frequency division signal and the logic level of each of the sub frequency division signals do not match, the logic level of the reference frequency division signal is set to the logic level of the sub frequency division signal that does not match. The input of the clock signal to the microprocessor that outputs the sub-divided signals that do not match is cut off until they match, and the phase of the reference frequency-divided signal and the phase of each of the sub-divided signals are made to match. This is a parallel synchronous operation control method.

Therefore, it is possible to match the phase of the reference divided signal and the phase of each sub-divided signal by a simple method using a clock signal, so the operation timing of each microprocessor can be controlled by keeping the same phase. This can be done using a branch signal, and each microprocessor can be operated in parallel and synchronously by synchronizing with machine cycles.

Next, this invention will be explained with reference to the drawings from FIG. 1 onwards showing an embodiment thereof.

In FIG. 1, (11 and (2+) are first and second microprocessors each consisting of an 8085A processor manufactured by Intel Corporation, and a clock input terminal (xa) and an inverted clock input terminal are connected to the processor (1). (Xa),
l) Set input terminal (ra) and frequency division output terminal (o
a), and the processor (2) is provided with a clock input terminal (xb) and an inverted clock input terminal (xb).
), an IJ upper set force terminal (rb) and a frequency division output terminal (ob) are likely to be provided.

When the 8085A processor inputs the clock signal shown in Figure 2(a) to the clock input terminal and also inputs an inverted clock signal, which is the inverted clock signal, to the inverted clock input terminal, the built-in frequency divider circuit operates. ,
As shown in the same figure (b), a frequency-divided signal with a waveform obtained by dividing the clock signal by two is output from the frequency-divided output terminal, and
The processor operates in synchronization with the frequency-divided signal, as shown in FIG.
As shown in FIG. 8, for example, when a reset signal of logic 0 (hereinafter referred to as 1ゝo'') for a reset command is input to the reset input terminal at the time of ja, the divided signal shown by the solid line 8a in FIG. A reset signal is fetched in synchronization with a change in , that is, the first fall of the frequency division signal from logic 1 (hereinafter referred to as 111+7) to "0" after time ta, and the processor is initially reset, In synchronization with the change in the frequency division signal shown by the solid line Sb in FIG. 6(b), that is, the change in the frequency division signal rising again from 110" to 11", the processor changes as shown at time tb in FIG. A reset display signal of "1", that is, a signal indicating that the device is in a reset state, is output from a reset output terminal (not shown).

Furthermore, as shown in FIG. 2(C), the reset signal is cut off at time tc, and the level of the reset input terminal becomes 110.
When rising from "to '1", the solid line Sc in the same figure (b)
The cutoff of the reset signal is detected in synchronization with the change in the frequency division signal shown in FIG. The change in the frequency division signal shown in Sd, that is, the frequency division signal is 0.
In synchronization with the rise again from `` to ゝゝ+II, the 11 + 77 reset display signal from the reset output terminal is cut off as shown at Ld in FIG. Start execution from the beginning of the program.

In FIG. 1, (3) is a clock oscillator that outputs the clock signal CK to the clock input terminal (xa) of the processor (1), and (4) is the inverted clock of the processor (1) that inverts the clock signal OK. The first inverter outputs an inverted clock signal to the input terminal (xa), and (5) is an exclusive NOR gate (hereinafter referred to as ENR) to which the frequency-divided signals Cm and Cs of both processors (1) and 12) are input. , (6) is a first flip-flop to which the output signal Ga of ENR (5) is input to the data input terminal (da), and the clock signal OK is input to the trigger input terminal (ta). (7) is an AND gate in which the clock signal OK is input to one input terminal, and the output signal of the Q output terminal (C1, a) of the flip-flop (6) is input to the other input terminal, and the output Signal processor (2)
This is a second inverter that inverts the output signal of the hend gate (7) which is output to the clock input terminal (XI) of the processor (2) and sends it to the inverted clock input terminal (xb) of the processor (2).

Still, (9) is a NOR gate whose input terminals are connected to the divided output terminals (b'il) and ('o"b) of both processors fil, f2+, respectively, and qO is a NOR gate (9)
The second output signal is input to the gate input terminal (bb).
It is a flip-flop, and its Q output terminal (qb) is connected to the reset input terminals (17a) and (ib) of both processors fll and f2, respectively.

Furthermore, (1]) is a reset section having Schmitt circuits 0 to 1, and the output terminal of the Schmitt circuit (13) is connected to the data input terminal (db) and clear terminal (Ol> of the flip-flop (10), and the Schmitt circuit Oz The input terminal of is grounded via the reset switch (13) and connected to the power supply terminal αC via the resistor (14).The capacitor 09 is connected in parallel to switch a:+.
A resistor Q4) and a capacitor (a time constant circuit when turning on the wrinkle stain source are formed, and a resistor Q4) is provided.
) is provided in parallel with a diode M.

Then, when the power is turned on, the clock oscillator (3) operates, and as shown in FIG.

3 o'clock, C4 o'clock, 5 o'clock... A clock signal CK with a period Ta varying from 110" to "X1" is output from the clock oscillator (3), and the clock signal is OK.
is input to the clock input terminal (Xa) of a predetermined processor, that is, the processor (1), and the clock signal OK is inverted by the inverter (4).
), an inverted clock signal is inputted toward the inverted clock input terminal of the processor (1), and from the branch output terminal (Oa) of the processor (1), as shown in FIG.
hour, L4' hour.

...inverted from ゝゝ0'' to ゝゝ1'' in each case, and at C3', 151 o'clock, ... respectively ゝ11''
A frequency-divided signal with a period Tb inverted from 110It to 110It, that is, a reference frequency-divided signal Cm is output.

On the other hand, at time u and time C2, the logic level of the reference frequency divided signal C is 11O", and as shown in FIG. Since the logical level of the frequency-divided signal, that is, the sub-frequency-divided signal C8, is also l0'', ENR (51 has a reference frequency-divided signal Cm of 10'', !: a sub-divided signal of 0'') Os is input, and since the logic levels of both branch signals Cm and Cs match, the ENRf5)'7) output signal Ga becomes 111''.

Also, C1 o'clock, C2 o'clock, 3 o'clock, C4 o'clock, 5 o'clock,
・From 0 to 1 of the clock signal GK in each
The flip-flop (6) is triggered by the rising edge of ゞl'', and the output signal Ga transmitted to the data input terminal (da) is latched into the flip-flop i6).

When C2, from the Q output terminal (qa) to the AND gate (7)
An output signal of ゝゝ1'' is output.

Therefore, as shown in FIG. 3(d), the two-cycle clock signal OK is sent to the processor [2] via the AND gate (7).
The clock signal OK is input to the clock input terminal (xb) of the processor (2), and the clock signal OK via the AND gate (7) is inverted by the inverter (8), and from the inverter (8) to the inverted clock input terminal (xb) of the processor (2). , an inverted clock signal obtained by inverting the clock signal OK is input, and a sub-divided signal Cs starts to be output from the frequency-divided output terminal (ob).

However, since the phase of the reference frequency-divided signal Cm is different from the phase of the sub-frequency-divided signal, the logic level of the reference frequency-divided signal Crn is As it becomes ``1'', the logic level of the sub-branch signal O8 becomes 110'', and the output signal of ENR (5) becomes ``0''.
become.

Therefore, at 1;3, the output signal of the Q output terminal (9a) of the flip-flop (6) becomes ``0'', and as shown in FIG.
As shown in d), during one cycle from 3 o'clock to 4 o'clock, the clock signal OK from the AND gate (7) to the processor +21 is cut off, and the sub-divided signal Os is kept at 0. be done.

As shown in FIG. 3(b), at t4, the reference frequency-divided signal Cm is not 0'', and the logic level of the reference frequency-divided signal Cm and the logic level of the sub-frequency division signal Cs match. ,
As shown in FIG. 4(d), the AND gate (7) outputs the quack signal OK to the processor (2) again, and at this time, the phase of the reference frequency division signal Cm and the phase of the sub frequency division signal Os are the same as the clock signal. Since they coincide at the timing of the signal OK, both branch signals Can and Os change in the same phase after L4, as shown in FIG.

On the other hand, when the power is turned on, the input of the Schmitt circuit o2 becomes 0'', so for a predetermined time determined by the resistor α (a), the capacitor (lυ) and the Schmitt circuit 0, as shown in Fig. 3 (e
), the Schmitt circuit (12 output signals Gb
is held at 110LL, and the output signal Gb of the Schmitt circuit o2 is 1"O", so the 27th lip-flop r
+□ is cleared, and as shown in the same figure), the output signal G of the Q output terminal ((Ib) of the second flip-flop rlO
d is held at ゝゞo'', and both processors fl), (
2+ reset hexagonal terminals (Ra) and (Rb) with “0”
The reset signal is removed.

Note that the above-mentioned predetermined time is set to be sufficiently longer than the time it takes for the phases of both the branch signals Crn and Os to match.

After a predetermined period of time has elapsed, as shown in FIG. 3(e),
Output signal G of Schmitt circuit α at time tx after time t5
When b changes from ゝゝ0'' to ゝゝ1'' and the reset of flip-flop fIO is released, (b) in the same figure, <
c> As shown in each figure, due to the initial change of both branch signals Cm and Cs from ゝゝ1'' to ゝゝo'' at time ty after time tx, the output signal of the NOR gate (9) changes to ゝゞo''. It changes from ゝゝ1〃, the top of the flip-flop is triggered, and at this time, the data input terminal (db) of the flip-flop +'l□ is connected to the Schmitt circuit ゝIL.
Since the L output signal %Gb is input, the output signal Gd of the Q output terminal (qb) at tz is
1'', and the reset signals of both processors m and (21) are simultaneously cut off, as shown in FIGS.

(At tz' after the 2+ reset signal is cut off,
Both branch signals Crn and Os change from 1ゝ0'' to ゝゝ1'' at the same time.
, the cutoff of the reset signal is detected in synchronization with the change of both branch signals Cm and Os from ``10'' to ``1'', and both microprocessors fil, +21 simultaneously start from the beginning of the input program. Start running.

Furthermore, when the reset switch α is operated, both processors operate in the same manner as described above.1), 12)
The reset signals of both processors (1
1, (simultaneously from the beginning of the program where 21 is input)
4 Start running.

Therefore, according to the embodiment, the ENR (5), the flip-flop (6), and the AND gate (7) can generate the reference frequency divided signal C by a simple method using the clock signal OK.
It can be controlled so that the phase of An and the phase of the sub-divided signal Cs match, and the resets of both processors ill and (21 are simultaneously canceled by the NOR gate (9), flip-flop (1o), and reset section (11). ,
It is possible to synchronize the machine cycles of both processors +11 and +21 to start executing the input program at the same time, for example, both processors fl),
It is possible to configure a parallel redundant system with a high failure detection probability of +21 and improve reliability.

In addition, in the embodiment, two processors m and f21
However, when applying to three or more processors, increase the number of synchronization circuits consisting of ENRf5), flip-flops (6), and AND gates (7), and increase the number of synchronous circuits of the Noah gate (9). Just increase the number.

[Brief explanation of drawings]

The drawings show an embodiment of the parallel synchronous operation control method of the present invention, in which FIG. 1 is a block diagram, FIGS. 2(a) to 2(d) are timing charts for explaining the operation of the microprocessor in FIG. 1, and FIG. 3(a) to 3(f) are timing charts for explaining the operation of FIG. 1 when the power is turned on. fll, r2+ microprocessor, (3)...
・Clock oscillator, (5)...Exclusive Noah gate, (6), rl[)...Flip-flop, (7)...And gate, (9)...Noah gate, 0 sword...・Reset part. Agent: Patent Attorney Ryutabe Fujita

Claims (1)

[Claims] ■ In a parallel synchronous operation control method for operating a plurality of microprocessors in parallel and synchronously, dividing an input clock signal by a built-in frequency dividing circuit to form a divided signal for controlling operation timing, The clock signal is input to a predetermined microprocessor, and a reference frequency division signal consisting of the frequency division signal of the predetermined microprocessor and a sub-frequency division signal consisting of the frequency division signal of each of the side microprocessors are input. When the logic level of the reference frequency division signal and the logic level of each of the sub frequency division signals do not match by comparing the timing of the zoh'c old record and tsuku signals,
cutting off the input of the clock signal to the microprocessor that outputs the sub-divided signal that does not match until the logic level of the reference frequency-divided signal matches the logic level of the sub-divided signal that does not match; A method for controlling parallel synchronous operation, characterized in that the phase of the signal is matched with the phase of each of the sub-divided signals. ■ When the power is turned on and a reset operation is performed, when the phase of the reference frequency division signal matches the phase of all sub-frequency division signals, a reset signal is input to each microprocessor, and the microprocessor 2. The parallel synchronous operation control method according to claim 1, wherein the reset is canceled at the same timing synchronized with the frequency signal.