JPS5952428A - Pilot signal generating circuit - Google Patents

Abstract

PURPOSE:To compose a relatively large-scale circuit of general logical circuits, by switching one counter successively for a change in frequency division rate and generating a 4-frequency pilot signal from one reference signal, and generating a timing pulse group whose phase error is suppressed to the precision of the reference signal as the 2nd reference signal. CONSTITUTION:A 378 fH reference signal CLK is supplied to a 4-frequency pilot signal generating circuit 1, the 5th pilot signal f5 generating circuit 2, and a PG edge detecting circuit 3. An f5 record timing pulse f5 generating circuit 2, an f5 reproduction timing pulse f5 PB, and an output control signal CNT control a pilot signal output circuit 4 so that pilot signals f1-f4 are continuous or intermittent waves. A timing pulse generating circuit 6 outputs two recording head switching pulses REC.HSW1 and REC.HSW2, a reproducing head switching pulse PB.HSW, an f5 recording timing pulse f5 REC, and an f5 reproduction timing pulse f5 PB as the timing pulse group.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a pilot signal generation circuit in a tracking system of a magnetic recording/reproducing device C (hereinafter referred to as VTR).
%, it relates to a circuit f that generates timing pulses such as a pilot signal for tracking control and a head switching signal (14SW signal).

Conventional structure and its problems In recent years, VTRs have become denser, and the width of the recording magnetization trajectory (
There is a strong tendency for the track width to become narrower. U Tracks are ideally recorded in a straight line on a magnetic tape, but in reality, due to variations in mechanical sound τυ degree, etc. F is recorded with f-specific curvature. For this reason, when performing compatible playback in which a magnetic tape recorded on one deck is played back on another deck, the inherent bending difference between the two decks cannot be corrected using control using conventional control signals. The playback quality deteriorates accordingly. This problem becomes more serious as the track width becomes narrower. To solve this problem, if K can obtain a tracking error signal corresponding to the track curvature, it is sufficient to displace the rotary head in the direction of the rotation axis in accordance with this error signal. As a method for displacing the rotary head in the direction of the rotation axis, a method using an electro-mechanical transducer composed of a piezoelectric element is well known, and its explanation will be omitted here.

By the way, there is a method Vf of generating a tracking error signal according to the above-mentioned track curvature, and a method of using a pilot signal for tracking control (hereinafter referred to as a pilot signal for the vehicle). In this method, a pilot signal is recorded h1 by being superimposed on a video signal, and during playback, the pilot signal is reproduced as a crosstalk signal from an adjacent track. and the direction of deviation. Various methods have been proposed for detecting a tracking error signal using pilot signals, ranging from a method using one type of pilot signal to a method using four types of pilot signals (four-frequency pilot signals).

OBJECTS OF THE INVENTION The present invention includes a circuit that generates a signal 'lft+fs+f4 shown in Table 1 below, which is used in a tracking method c (hereinafter referred to as 4-frequency tracking method) using a 4-frequency pilot signal. Note that the present invention is directly related to the four-frequency tracking method, so a description thereof will be omitted.

Table 1 However, fH is the horizontal synchronization frequency (line frequency).

Since the tracks are directly adjacent to each other, when recording, V is
Each head must be lined up in the correct position relative to each other. However, there is an error due to the hysteresis of the transmutation element, etc., and during recording, the pJ of each head is
Since no permanent weighing conditions occur, the required full +1fll signal, which is necessary to control the relative position of the heads during recording, is applied periodically during a short period at the beginning of each track. 4H can be obtained by setting mil. This measurement is performed by recording the signal at a frequency of about 228 for a period of about one line, and switching to playback for the next period of about one line, f, the signal obtained from the previous track on which the signal was recorded. and measure its amplitude. The measurement results of each head are compared and the relative positions of the heads are controlled so that the results are equal.) 1 is sufficient.

Furthermore, the f5 signal is set as the second reference signal Cf, GK), and ■
The recording head switching pulse (RFC, H8W,) (R'ffJC-
H8W2) and head switching pulse for playback (:
pB, asw), f5 recording timing pulse (f, RKC) and f, reproduction timing pulse (fij'B) for the head relative position control are set to accurate pulse period j using a counter circuit or the like. It can be generated as a useful pulse.

4-frequency pilot signals (fl) to (f4) in Table 1 above
One possible way to obtain an accurate value is to use four oscillation circuits, but there are disadvantages such as high cost.
There is a case.

Another method is to provide one reference oscillation circuit having a common multiple of four frequencies and generate a four-frequency pilot signal using a frequency dividing circuit. This method is useful in that the variable oscillation circuit for extracting the jitter of the reproduced color signal can also be used as a reference signal (CLK) oscillation circuit, and its value is 37.
When the reference signal (CLK) is 378 fa, the stiffness is 1158, 1150, 1/40, 1/
If the frequency is divided by 36 K, fl 1 f2+ fS ; f4 in Table 1 above is obtained, corresponding to Towara's frequency division ratio.

Further, the f signal used for controlling the relative position of the head is also obtained by dividing the frequency of the reference signal (cbx) into f1/26.

Furthermore, by using the f5 signal as the second reference signal (f, CK) and using a counter circuit, a decoding circuit, etc., each required timing pulse can be obtained.The first object of the present invention is to use one reference signal (CLK), one counter is sequentially switched to change the frequency division ratio to create a four-frequency pilot signal, and another counter is used to generate a signal from the first reference signal (CLK). Make this f,
The object of the present invention is to provide a means for creating a timing pulse group whose phase error is suppressed to the accuracy of the reference signal (CI, K) by using the signal as a second reference signal (f, CK).

The second purpose is to output the 4-frequency pilot signal as a continuous wave, or to output the 4-frequency pilot signal as f5.
recording timing pulse (f, REC) and f.

Outputting the f5 signal as an intermittent wave with an average DC level only during the M main timing pulse (f, PB) period, and making the f5 signal an intermittent wave only during the f5 recording timing pulse (f, RKC) period;
In order to achieve the above object, the present invention provides a means for outputting the signal as a high impedance during other periods, and a means for mixing the 4-frequency pilot signal and f signal output in an intermittent wave. The pilot signal generation circuit includes a 4-frequency pilot signal generation circuit that frequency-divides the first reference signal to generate pilot signals of four types of periods, and a 4-frequency pilot signal generation circuit that frequency-divides the first reference signal to generate pilot signals of four different periods. A signal generating circuit for generating a double signal (f), a head switching pulse for recording and reproduction as a second reference signal for the f, double signal, and a raw timing for recording and reproducing the f, double signal. This configuration includes a timing pulse generation circuit J that generates pulses.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below based on 12 pages.

FIG. 1 shows block 1si1 of the pilot signal generation circuit. 378 fi base 1m No. 18 (CLK) is a 4-frequency pilot signal generation circuit (1), f5 generation circuit (2)
, and the PG edge detection circuit (3) K is supplied.
The four-frequency pilot signals (f,) to (f4), which are the outputs of the frequency pilot signal generation circuit (1), are pilot signals and
This pilot signal output circuit (4)K is supplied with f, recording timing pulse (f,
RFC) and f.

Reproduction timing pulse (f, P:l and output control signal (
CNT) is supplied, and pilot signals (fl) to (
The output of f4) can be controlled to be a continuous wave or an intermittent wave. The f signal output from the f6 generation circuit (2) is:
f.

Output circuit (5) K is supplied.
1K is the f, recording timing pulse (f, RPC
) and output control signal (CRT) are supplied, ffl
The signal output is controlled to be a fully continuous wave or an intermittent wave. The f5 signal output from the flI generation circuit (2) is the second
A timing pulse generation circuit (6) K is supplied as a reference signal (f, CK) for the timing pulse generation circuit (6), and two recording head switching pulses (RBC, H2N, ) (RKC-H2N, , )
and head switching pulse for playback (FB, H2N)
and s fI + recording timing pulse (fsREC),
A timing pulse group of fl+reproduction timing pulse (fIIFB) is obtained. The reproduction head switching pulse (PE-H2N) H, 41iS wave high 0t signal (
fl) to (f4) are used as switching signals to switch the I+i order, and are fed back to the 4-frequency pilot signal generation circuit (1), f, recording timing pulse (f5RFIC) [pilot signal output circuit (4) and f, output circuit ( 51K
, also f, reproduction timing pulse (fIIFB) l
d are fed back to the pilot signal output circuit (4). A PG double signal is supplied to the PG edge detection circuit (3), and the detected PG edge is used as a reset signal for the fI+ generation circuit (2) and as a timing pulse generation circuit IN.
Figure 2 shows a specific circuit example of the 4-frequency pilot signal generation circuit (υ) and the pilot signal output circuit (4), which is supplied as the operation start signal of '6 (6). 2 is a waveform diagram of each part of the circuit shown in FIG. 2. In addition, in FIG. 3, CHT, f, REC,
This is the signal waveform in the case of f, PB == Hlgh, and it is also the signal waveform when viewed at a period several hundred times more than L+11z in Figure 4.
)(1) The shaded part is the signal shown in Figure 3 (g>(h)
(i) The waveform is a continuous wave.

A reference signal (CLK) is supplied from the terminal (7).

(8) is a programmable counter (hereinafter referred to as a 4-frequency counter), and the reference signal (CLK) is (l + ten &)
Every time a count is made, a pulse is generated and the output signal (a) is converted to (N, this output signal (a) from K to a 4-frequency counter (8
) to reset the KMN'j, and the third
As shown in the figure, the output signal (a) is a 6 or 4 frequency counter (8
The output signal (1)) of ) is obtained by generating a pulse every time the reference signal (CLPC) is counted.
Output signal (a) to output signal (1) as shown in Figure 3 f)
The period up to #Le+ is reached. (9) This is a reset set flip-flop C (hereinafter referred to as R8-FF), which is set by the output signal (a), reset by the output signal (b), and outputs the signal (C). It is a T-type flip-flop C (hereinafter referred to as T-FF) and outputs the signal (d). till ++21 is an AND circuit, Re-FF
+91 Q output (signal (C)) and T -FF (]
The signals (e) and (f) are output as respective AND outputs with the Q and Q outputs of 0 (signal (d) and its inverted signal).・, +3t ~ α6) is a NAND AND circuit, signal (e) is a NAND circuit 1131 ++4), and a signal (
f) NANDAND circuit) 'fl supplied to Jul. On the other hand, the output control signal (CNT) is inverted by lη, and the inverted signal (CNT) is supplied to the NAND AND circuit 135.
f, an inverted signal (f, REC) in which the recording timing pulse (f, REC) is inverted by the inverter (+81), and f5 an inverted signal (f, REC) in which the reproduction timing pulse (f, PE) is inverted by the inverter α. (CNT-f, RBC-f, FB) VtiAND which is the output of the AND circuit (20).
It is supplied to the circuit t+41 +161. Furthermore, the output of NAND circuit 03) (14) is 11JAND circuit 121!
K, the output of the NAND circuit 1151161 is AND
When the circuit zf is supplied, the signal (g) which is the output of the NAIJD circuit 211 and the signal (g) which is the output of the AND circuit 2)
hl tfi looks like this:

■ CNT = Low j, base (4th and 1st area (a)) Therefore @ CNT = High, f, REC-f, PB = -H
igh” alignment (region 4M (b)) Therefore, in the case of this 0 term, the signal (g) (h) (/If is the same as in the case of 0 term, and the repeating waveform of the waveform shown in Fig. 3 becomes.

θ CNT=H1gh, f, RFiC=H1gh or f
, FB = H1gh (region (c) in FIG. 4).

t2311241 is an electronic switch, signal (g)
When (h) is High, it is connected to the power supply voltage VDD side, and when it is Low, it is connected to the ground side. Signal (g) = H1ghl When signal (h) = Hlgh, the level vH of output signal (1) is R.

VH==, 7 ÷ ÷ partner・VDD...■. Also, when the signal (g)=Low, the signal (g)=Low, it is output. Also, signal (g) = LOW, signal -1 (hl =
Hlgh (or signal (g) = Hlgh, signal (h
)=Low) At the time of (1), the output signal (1) becomes a constant value, vno. Furthermore, from the above formula 00, vH'%' sub=VDD vI.

2 2 ... ■ Or VH+VL= VDD --
- ■ is established, and the signal (1) has a 316 waveform with the same size from VDD/2 to vH and from VDD/2 to vTJ, and a waveform with good symmetry is obtained. 't4 frequency pilot signal (f,) ~ (f4)
This is useful for removing harmonics of □, but its explanation will be omitted here.

Fig. 5 shows four frequencies f at four frequency channels 41 (8) K to obtain four types of pilot signals (fl) to (f4).
It is a circuit diagram showing an example of the switching circuit of 1 to f4, and the output of the 4-frequency counter (8) is the terminal of the switch (A,) to
(D,') and terminals (A2) to (D
2).

Switch=l=Il=12fil [2f31 are interlocked with each other, (A,) and (A2), (B,) and CB,),
The combination of terminals (C7) and (C2), (D, ) and (D2) allows for 111M order switching. switch +251
1 t261 is the reproduction head switching pulse (F
B, H8W) and its -divided signal (-LpB, Hsw)
This relationship is as shown in Table 2 below.

Table 82 In the above Table 2, H is High potential and L is Low.
Shows the ii position. From Table 2 above, the pilot signal (f,
) to (f, ) are sequentially switched and output for each field. In addition, a 4-frequency pilot signal (f
, ) to (f4) are the waveforms of the third and first signals (1) and the output p
-h,.

Its period is (60 times 2) x'2, so 4 in Figure 5
It is shown as a fixed value of the frequency counter (81K (佑+4)), and the pilot signal (f,) (f,) (f
, > (f,) sets the reference signal (CLK) to 1158.1
It can be seen that the signals are frequency-divided to 150.1/36.1/40.

FIG. 6 shows a specific circuit example of the f6 generation circuit (2) and f6 and the output circuit (5), and FIG. 71 and FIG. 8 are waveform diagrams of various parts of the circuit shown in FIG. 6. The force in Figure 7 is CNT =
This is the signal waveform in the case of Low straddle CNT・f, RBC=Hlgh (1), and it is also the signal waveform when viewed at a period several hundred times longer than 13 in Figure 4.
The shaded part of the signal GA') (m) shown in i' is a continuous wave of the waveform of the signal (a (m)) shown in Figure 3. (2) A counter (hereinafter referred to as f6 counter)
Its output signal (j) is the base signal (CLK) of 4. It generates a pulse every time it counts, and from this signal (j) K, f and Calantare η are reset via an OR circuit group.
1 K As shown, the signal (j) has a repeating cycle of A's period.

Also, every few hundred times of the signal (j), the PG edge π resets the counter I2 through the front 110R circuit (281), so the signal (j) is output in synchronization with the PG edge. (29) is T-FF, and the signal (j)
The frequency is divided by 1/2 and a signal (k) is output. , T-FF
Q output (signal (k)) of (29) + NA1JD circuit +3
0) cll F supply subtracted, Cono NAND circuit +30
) CLLL is supplied to the NAND circuit Cl21. On the other hand, the output control signal (CNT) is inverted and inverted by the inverter, and the inverted signal (〒) is supplied to the WANDAND circuit. In addition, the output control signal (CNT), the recording timing pulse (f, REC), and the KAND circuit (3
4i, and the output of the AND circuit (34) is NAND
AND circuit 1K is supplied. The output of the NANDAND circuit is as follows.

@ CNT = Low ) 173 (area in Figure 8 (
A) When CNT = H1gh, f, RKC = H1gh (area (E) in FIG. 8) In the case of the above 00 term, the signal (effect) has a repeating waveform of the waveform shown in FIG.

θCN'r = Hl gh , fs REC = Lo
In the case of w (region (to) in Fig. 8).

The first length is an electronic switch, and a signal (0) is input.

Zheng) is an OR circuit, and the inverter state) output station and AN
D circuit)1 output CNT-f, REC is manually operated,
When either of the human power is )iigh, the output signal (n) of the OR circuit (:kan) becomes fdHlgh, and the electronic switch 1
351HON state, and its output signal (as ml,
When all the inputs of the signals (the same 'LJ number as 0 is obtained, but the OR circuit Zheng) are Low, the signal (n) which is the output of OR circuit 1 is also Low, and the electronic switch C (5) is turned off.
It enters the F state, and its output (m) reaches the state of an oven (, 6 impedance) (indicated by 2 in the region of FIG. 8). In addition, 1m is selected as a frequency division value of 13 counts, and the signal (the station is a reference signal (CLK) divided by 1/26,
It can be obtained as a rectangular wave signal with a duty of 50:50, and this signal (S (m) is f).

Figure 9: Specific circuit of PG edge detection circuit (3) V/11
Figure 10 shows the waveforms of each part of the circuit shown in Figure 9. The reference signal (CLK) is input to the input terminal (7), and the PG
The double signal is supplied to the input terminal 1. 1381139) is a D-type flip 7o tube (hereinafter referred to as D-FF), (
As shown in FIG. 8, the PG edge signal can be obtained as the output of the NAND circuit +43.

This circuit is generally well known and detailed explanation will be omitted.

FIG. 11 shows a specific circuit example of the timing pulse generation circuit (6), and FIG. 12 shows a two-channel tape pattern and waveforms of various parts of the circuit shown in FIG. 11 that have a phase relationship with each tape pattern. 1431
d AND circuit, this AND circuit 1431 K fs
(using signal (k) in Figure 6) and signal (q
) and counts the second reference signal (f, CK) to create each timing pulse. 145
) is a programmable decoder C (hereinafter simply referred to as a decoder), which decodes each bit output (12 to 13 bits) of the timing pulse counter (bamboo) and outputs (S
, )(S, uh...(R4) and (R,)(R1...
・(R4) (Output each count signal of R4.(S
, )(B,)(R,)(F3.)(R,)(84)(R
4) PO double signal rising edge (tape pattern (a)
It is a count signal starting from the 00 position of (S-
(R2su(R,')(E'j(R2u(R-(RIW)
PG double signal falling edge (tape pattern (b) 1
This is a count signal whose starting point is approximately 80 degrees W). The size relationship of these count governments is as follows.

SI' + R4''4' + 64
”'R3'S1< 82 < Tokou < 84 , R4 <
BB<R2<Ef4S,'<82'<R,'
<R3',S1'<Ss'<R,'< R3
'However, (R2) and (R3), (R,) and (nt
), (s 25 and (ss'Th.

The size of each combination of (R- and (R23) may be any size. Also, 52=S2' e RI-R1' +
SA"SS' + R2" may also be present -! 4 (a to 3+l are REI-y chill, p, each R8-F
F (7) Set terminal (S) and reset terminal (R)
K is the output of the decoder respectively (Sρ and (R, Th
, (S, (R4), (84) and (R3, (S, M
St and (R1) (R1, and (S s) (S, ut) are input in combination of R2 MR25 and shown in FIG. 12 as the output of each R8-FF (REC-HEIW,)
, (Inc-H8W,) , (PB, H8W) ,
Each timing pulse of (f, RFC) and (f, FB) is obtained, and the timing pulses of (f, RFC) and (f, FB) are obtained. (511 is an OR circuit, in which the count signal (R4') (RX is input, and the output signal (r) l- is indicated by the 12th material IK, f52
1 digit RB -FF, its set terminal (S), K's pa edge is the reset terminal (R), K's signal (r) is input -Ji, and the signal ((L) is obtained as its output. Signal ( ql is supplied as a reset signal for the timing pulse counter, and the signal (q) is Hl. During the GH period, the timing pulse counter (441) is active, and during the LOW period, it is reset and the count is stopped as is. The signal (q) is also supplied to the AND circuit 141, and when the signal ((1) is in the H1gh period, Kf,
The output signal is the second reference signal (f, CK) (Fig. 12, shaded areas f, CK)
is supplied to the timing pulse counter 1441K, and the above operations are repeated. In the above operation, the PG edge f detected with the accuracy of the reference signal (CLK)
The timing pulse counter IA4 operates using the second reference signal (f!1CK) which is r, +j as the reference number 1a.
) also starts operating in synchronization with the PG edge, so by using the second reference signal ('f, GK), which has a longer period than the reference signal (CLK), as a reference signal, the scale of the counter can be reduced, and the counter can be used as a reference signal. Bit errors can be suppressed by the accuracy of the signal (CLK).

8.112 In Figure 1, 0 of the tape pattern (a)
0.~31° period and tape pattern (b) 1800
The period from ~211° (shaded area) is applied to PCM audio and is excluded from the video signal and pilot I C track, so it is necessary to create the valley l timing pulse as described above. Also, tape pattern (a) 0
The 180° position of the tape pattern (B) has a phase relationship that allows them to be treated equally, and the 00 to 360°'r of these tape patterns (A) and (B) is
Figure 13 shows the four-frequency pilot signal obtained as signal (1) and the f5 signal obtained as signal (m). Circuit 17+ is a mixing circuit using a resistor,
FIG. 14 shows f, recording timing pulse (fsRFiC), and f5 reproduction timing pulse (f) when CNT=H1gh.

PB) and the waveforms of each part of the circuit shown in FIG. 13. A portion of this circuit is shown in FIG. Terminal 1531 K u ・Electronic switch (15
Signal (m) is supplied from Rt')(R
B) Compare K and choose the smaller value. During the f, recording timing pulse (f, RKC) period, the f, signal of the signal (m) is superimposed on the 'vnn level of the signal (1), and the signal (1 w 1 vDD is taken as an average value, approximately 0). The f5 signal has an amplitude of ~VDD. f5 reproduction time // pulse (f,
FB) period 11jH1f, since the signal (m) has high impedance, the signal (1') is as low as the VDD level of the signal (1), and (f, RKC) (f, F
During the period except B), since the signal (→ is high impedance), the 4-frequency pilot signal of signal (1) is output with the amplitude of v, , , VH as it is.In this way, As shown in Fig. 14, a signal (1) can be obtained by mixing the 4-frequency pilot signal and the f signal, and the resistor (R,) (R,) (R,') (R,) By choosing the resistance value, it is possible to easily determine the relative amplitude of the 4-frequency pilot signal at K and the signal f.
Only when r = H1gh, use a resistor (R4) to mix the 4-frequency pilot signal and f, signal, and CNT =
, it is assumed that the low setting and the resistor (R4) are not applicable.

As described in the detailed description of the invention, most of the parts of the pilot signal generation circuit according to the present invention, except for a simple resistor circuit in the output section, are constructed of general logic circuits. This makes it suitable for k108-type semiconductor integrated circuits (C), so relatively large-scale circuits can be manufactured compactly and at low cost.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram of a pilot signal generation circuit, FIG. 2 is a circuit diagram of a four-frequency pilot signal generation circuit and a four-frequency pilot signal output circuit, and FIG. Figures 4 and 4 are waveform diagrams of various parts of the circuit shown in Figure 2, Figure 5 is a circuit diagram of a four-frequency counter switching circuit, and Figure 6
The figure shows a circuit diagram of the IL signal generation circuit and the f5 signal output circuit, and Figures 7 and 338 show waveforms 1 of each part of the circuit shown in Figure 6.
Figures 1 and 9 are circuit diagrams of the PG edge detection circuit, Figure 10 is a waveform diagram of each part of the circuit shown in the 91st line 1F, the 11th factor is a circuit diagram of the timing pulse generation circuit, and Figure 12 is the tape pattern and Explanation of the relationship between the waveforms of each part of the circuit shown in FIG. 11. FIGS. 1 and 13 show the 4-frequency pilot signal and f! Figure 14 is a circuit diagram of a mix circuit that mixes CNT =
This is a clear diagram of the interrelationship between the 4-frequency pilot signal at H1gh, the f signal, and the mixed signal of these two signals. (1)...4-frequency pilot signal generation circuit, (2)...
... f5 generation circuit, (3) ... PG edge detection circuit,
(4)...Pilot signal output circuit, (5)...f
, Output circuit, (6)... Timing pulse generation circuit representative Yoshihiro Morimoto 172- Figure 3 Figure 4 Figure 5 ゛Figure 12 Figure t31'' j Figure 14

Claims (1)

[Claims] 1. A four-frequency pilot signal generation circuit that frequency-divides a first reference signal to generate pilot signals with four different periods;
a signal generation circuit f which divides the frequency of the first reference signal to generate a fifth pilot signal (hereinafter referred to as f, signal); A pilot signal generation circuit comprising a timing pulse generation circuit that generates a head switching pulse for reproduction and a timing pulse for recording and reproduction of the f5 signal. . 2. The 4-frequency pilot signal includes a first counter that counts a first reference signal, a first output signal that counts N cycles out of the output signal of this first counter, and N, less. A first flip-flop circuit whose output state changes depending on both signals of the second output signal counted by several N2 cycles, and an output state which is inverted every time the @'+1 signal is input. a second flip-flop circuit; a first gate circuit that processes the output signals of the first and second flip-flop circuits; and controls the first gate circuit to output one word continuously or intermittently. a second gate circuit that processes the control signal to obtain a signal for driving the first gate circuit; The first If element switch whose output is in the state of either the source voltage or the ground potential is driven by the output signal of the first If element switch and the output signal of this first element switch. A combination of 44 class count signals (N, A, N2A)
. (N1B, N,B), (N,C, N,C)
, (N, D, NtD). The pilot signal generating circuit according to claim 1, further comprising a switching circuit for controlling the first counter so as to produce , (N, D, NtD). 8, f. The signal generation circuit includes a second counter that counts the first reference signal, and a third counter that inverts its output state every time the output signal of the second counter that counts only NS cycles is input. 7 lip-flop, a third gate circuit for processing the output of the third 7-lip flop, a second electronic switch for opening and closing the output signal of the third gate circuit, and a second electronic switch for opening and closing the output signal of the third gate circuit; A control signal for controlling the second electronic switch to make its output a continuous signal or an intermittent signal, and a third gate circuit and a second gate switch for processing this control signal. a fourth gate circuit for obtaining a driving signal; and a fifth gate circuit for inputting an edge signal of the KPG signal as a reset signal for the second counter in order to synchronize the second counter with the PG multiplied signal. A pilot signal generation circuit according to claim 1, having a configuration comprising: Table 4. Processes the output signals of the fourth and fifth flip-flops, such as the fourth and fifth flip-flops, for detecting the rising and falling edges of the PG multiplied signal with the accuracy of the first base signal. 4. A pilot signal generation circuit according to claim 1 (4), comprising a PG edge detection circuit comprising a fifth gate circuit for detecting a PG edge signal. 5. The timing pulse generation circuit outputs the f5 signal, which is the output of the f5 signal generation circuit, to the second reference Q and the 30th counter that counts this second reference 1g, and the output of this third counter. A decoder is driven by the output signal of this decoder to output the first and second recording head switching pulses, reproduction head switching pulses, and the recording and reproduction timing pulse of No. 151g. The sixth to tenth flip-flop circuits are driven by the output signal of the decoder and the PG edge signal, and f! an eleventh 7-lip-flop whose output signal is a gate signal for gating the I signal to make it a second reference signal and at the same time synchronizing the third counter with the accuracy of the PG multiplier first reference signal; A pilot signal generation circuit according to claim 1, wherein the pilot signal generation circuit is configured to include a circuit. 6. Third and fourth gate circuits that output the fll signal only during the signal recording timing period and maintain high impedance during periods other than this, and a power source during the fI+ signal distribution and reproduction timing period. The first and second gate circuits control the voltage to be at a constant level of 1 and output a 4-frequency pilot signal only during other periods, and a large signal is output between each period. 2. The pilot signal generation circuit according to claim 1, further comprising a resistor for mixing the signal and the four-frequency pilot signal.