JPS5953941A - Information processing device - Google Patents

Information processing device

Info

Publication number
JPS5953941A
JPS5953941A JP57164476A JP16447682A JPS5953941A JP S5953941 A JPS5953941 A JP S5953941A JP 57164476 A JP57164476 A JP 57164476A JP 16447682 A JP16447682 A JP 16447682A JP S5953941 A JPS5953941 A JP S5953941A
Authority
JP
Japan
Prior art keywords
error
circuit
signal
time monitoring
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57164476A
Other languages
Japanese (ja)
Other versions
JPH0218506B2 (en
Inventor
Akira Jitsupou
実宝 昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57164476A priority Critical patent/JPS5953941A/en
Publication of JPS5953941A publication Critical patent/JPS5953941A/en
Publication of JPH0218506B2 publication Critical patent/JPH0218506B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To minimize te influence exerted on performance, and to raise reliability and a maintenance property of a device, by providing a means for inhibiting or releasing the generation of an error report signal, and discriminating whether a correctable error is a fixed fault or a temporary fault. CONSTITUTION:In case when a correctable error is detected by an error detecting and correcting circuit 2, ''1'' is added to contents of an error generation frequency storing circuit 5 by a detecting signal 34 for reporting said detection. Subsequently, a value 36 of correctable error generation frequency of the circuit 5 is compared with an initial set value 38 of an error threshold circuit 6 by a comparing circuit 7. When they coincide with each other, an error report is inhibited by an error report controlling circuit 9. Subsequently, a time monitoring signal 41 is outputted to a time monitoring circuit 8 from the circuit 9, its initial set value 43 is subtracted by ''1'' each in accordance with the signal 41, and when its value is reduced to ''0'', a monitoring end signal 40 is generated and is inputted to the circuit 9. The circuit 9 refers to the value 36, and releases the inhibition of the error report if a value of correctable error generation frequency in the course of the time monitoring is ''0''.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は上方処理装置、特に制御記憶装置からの読出し
データのエラー自動訂正機能を有する情報処理装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an upper processing device, and particularly to an information processing device having an automatic error correction function for data read from a control storage device.

〔従来技術〕[Prior art]

ストアドブログラム方式を採用する情報処理装置におい
ては、命令の読み出し、命令の解読、解読した命令の実
行という一連の動作を繰り返すことにより所定の処理が
実行される1、これらの動作は、すべて、レジスタ間の
情報の転送、シフト前作、加算器の使用など数十種の基
本動作のnlみ合せによって実行できる。
In an information processing device that uses a stored program method, a predetermined process is executed by repeating a series of operations: reading an instruction, decoding the instruction, and executing the decoded instruction1. It can be performed by combining dozens of basic operations, such as transferring information between registers, shifting beforehand, and using adders.

そのような基本動作を指定する指令をマイクロ命令とい
い、これを組合わせて各命令の実行を行うものがマイク
ロプログラム制御方式による情報処理装置である。
Instructions specifying such basic operations are called microinstructions, and an information processing device using a microprogram control system is one that executes each instruction by combining these instructions.

マイクロ命令は、情報処理装置の制御に前接関係するも
のであるので、マイクロ命令を制御記憶装置から読み出
す時には、従来よυ1ビットエラー検出訂正及び2ビツ
トエラー検出の機能をもった誤シ訂正技術が採用され、
広く一般に用いられている。従って通常運転時に(づ5
、訂正可能エラーを検出するとこれを訂正して、訂正済
データによυ動作を続行可能なように構成されている。
Since microinstructions are related to the control of an information processing device, when reading microinstructions from a control storage device, conventional error correction technology with functions of υ1-bit error detection and correction and 2-bit error detection has been used. Adopted,
Widely used. Therefore, during normal operation
, when a correctable error is detected, it is configured so that it can be corrected and the υ operation can be continued using the corrected data.

従来、この種の情報処理装置では、」正可能なエラーが
1回もしくは数回検出され訂正されると、その時点でエ
ラー報告信号を発生して、エラーの発生した制御記tt
の該当アドレスおよびビット位置等に関するエラーログ
情報が収集され、以後、ニジ−報告信号の発生を抑止す
るという方法をとっていた。
Conventionally, in this type of information processing apparatus, when a correctable error is detected and corrected once or several times, an error report signal is generated at that point, and the control record in which the error occurred is
Error log information regarding the corresponding address and bit position of the error log is collected, and the generation of the error report signal is subsequently suppressed.

エラー報告信号発生時の障害が固定的な障害であれば、
以後エラー報告信号の発生を抑止する方法は、不必要な
エラーログ情報をとることによる性能低下を防ぐという
点で有効でおるが、一時的な障害であれば、以後有効な
エラーログ情報が全くとられないという欠点があった。
If the failure when the error report signal occurs is a fixed failure,
The method of suppressing the generation of error report signals from now on is effective in preventing performance deterioration due to collecting unnecessary error log information, but if the failure is temporary, no valid error log information will be available from now on. There was a drawback that it could not be taken.

〔発明の目的〕 本発明の目的は、エラー報告信号発生後、エラー(・ド
告佃号の発生を抑止するとともに、あらかじめ設定され
ていた一定時間内に工2−訂正がなりたば、エラー報告
信号発生の抑止を5IP(除する手段を設けて訂正可能
なエラーが、一時的な]障害か固定的な障害かを区別す
ることにより上記次点を解決し、1li1.! :n記
1首装置から読み出したマイクロインストラクションの
訂正可能なエラーが[151定11蹟害でおれば、以後
エラーの訂正のみ実施し、不必要なエラーログ情報をと
ることを止め性能に与える影響を極力小さくして、ニジ
−が一時的な障害ならエラーログ情報の収集を継続する
ようにしたより高い信頼性、保守性を備えた情報処理装
置−葡提供することにある。
[Object of the Invention] The object of the present invention is to prevent the occurrence of an error (*) after the error report signal is generated, and to prevent the error from occurring if the error is corrected within a predetermined period of time. The above runner-up problem is solved by distinguishing between a temporary failure and a fixed error, which can be corrected by providing a means to divide the suppression of report signal generation, and 1li1.!: n-1 If the correctable error in the microinstruction read from the neck device is [151-11], from now on, only the error correction will be performed, and unnecessary error log information will be stopped to minimize the impact on performance. Therefore, it is an object of the present invention to provide an information processing apparatus having higher reliability and maintainability, which continues collecting error log information even if the error is a temporary failure.

〔発明の構成J 本発明は制御記憶装置にマイクロプログラムを    
 □ロードし該マイクロプログラムを順次読み出してデ
ータ処理を行なう情報処理装置において、前記制御記憶
装置からのマイクロインストラクション読み出し時に読
み出されたマイクロインストラクションデータのエラー
を検出する手段と、検出したエラーが訂正可能なエラー
であれば前記データを訂正する手段と、前記エラーの訂
正回舷とあらかじめ設定された値とを比較して一致すわ
ばエラー報告信号を発生する手段と、前記エラー報告信
号発生後は前記エラー報告信号の発生を抑止する手段と
、あらかじめ設定された一定時間内に新たなエラーの訂
正があればエラー報告信号を発生してその後(伏凋、び
前記エラー報告信号の発d−を抑止する手段と、新/ζ
なエラーの側圧がなければ前記エラートラ告信号発坐の
抑止を解除する手段とを含んでM!霞]さハる。
[Configuration of the Invention J The present invention stores a microprogram in a control storage device.
□In an information processing device that performs data processing by sequentially reading out microprograms, there is provided a means for detecting errors in microinstruction data read out when reading out microinstructions from the control storage device, and a means for detecting errors that can be corrected. means for correcting the data if an error occurs; means for comparing the error correction speed with a preset value and generating an error report signal if they match; means for suppressing generation of an error report signal; and means for generating an error report signal if a new error is corrected within a preset certain period of time, and suppressing generation of the error report signal after that (decrease); and new/ζ
and means for canceling the suppression of the error notification signal generation if there is no side pressure of an error. Kasumi] Saharu.

〔実施例の屹明〕[Examples of examples]

次に本発明について1面を参11工して詳細1に説す1
」する。
Next, the present invention will be explained in detail in Section 1 after referring to page 1.
"do.

第1σ1は本発明の一実施例のブロック図で、1はマイ
クロプログラムなN11憶する制御記+AV、+装置、
2は制徊I記憶↓l′、9聞1からの1元出しデータ3
0のエラー検出および自動訂正を行う訂正回路、3は前
記読出しデータ30とエラー発生時に訂正回路2によっ
て訂正されたデータ32とを訂正可能エラー検出信号3
4の制御によって切替える切替回路、4は前記切替回路
3の出力33から得られるマイクロインストラクション
によって制御され、主要な演算および装置全体の制御等
を行う演q部(本演算部4によって、次に読出されるべ
きマイクロ 2インストラクシヨンのアドレス31も生
成される)、6は外部の診断プログラムなどによって与
えられる値37によって初期設定することができるエラ
ースレッショルド回路、5は前記訂正可能エラー検出信
号34によってその内容が1づつ加咎されるエラー発生
回数記憶回路、7はエラースレッショルド回路6からの
出力38とエラー発生回数記憶回路5からの出力36を
比較して、一致すれば一致信号39を発生する比較回路
、9は一致信号39により、エラー報告信号42を発生
ずるとともに以後エラー報告信号42の発生を抑止する
エラー報告制御回路、8は外部の診断プログラムなどに
よって与えられる値43によって初期設定することがで
きる時間監視回路である。また41はエラー報告制御回
路9から時間監視回路8に起動を指示する時間監視指示
信号、40は時間監視回路8から、時間監視終了をエラ
ー報告制御回路9に報告する時間監視終了信号、35は
時間監視回路8に時間監視指示信号41によって時間監
視の開始が指示されるとエラー発生回数記憶回路5の内
容をリセットすることを指示するカウンターリセット信
号である1、 本装にの通常の動作時は、アドレス31に従って制御記
憶装置1から読出されたマイクロインストラクションデ
ータ30が、切替回路3を経由して演算部4の制御に用
いられる。
The first σ1 is a block diagram of an embodiment of the present invention, where 1 is a microprogram N11 storing control memory +AV, +device,
2 is control I memory ↓l', 1 source data 3 from 9th sentence 1
0 error detection and automatic correction, and 3 is an error detection signal 3 capable of correcting the read data 30 and the data 32 corrected by the correction circuit 2 when an error occurs.
A switching circuit 4 is controlled by the microinstruction obtained from the output 33 of the switching circuit 3, and is connected to an operation section (the operation section 4 that performs the main calculations and control of the entire device, etc.). 6 is an error threshold circuit that can be initialized by a value 37 given by an external diagnostic program or the like; 5 is an error threshold circuit that can be initialized by a value 37 given by an external diagnostic program, etc. An error occurrence count memory circuit 7 whose contents are incremented by 1 compares the output 38 from the error threshold circuit 6 and the output 36 from the error occurrence count memory circuit 5, and if they match, generates a match signal 39. A comparison circuit 9 generates an error report signal 42 based on the coincidence signal 39 and an error report control circuit that suppresses generation of the error report signal 42 thereafter; 8 initializes with a value 43 given by an external diagnostic program or the like; This is a time monitoring circuit that can Further, 41 is a time monitoring instruction signal from the error report control circuit 9 to instruct the time monitoring circuit 8 to start, 40 is a time monitoring end signal from the time monitoring circuit 8 to report the end of time monitoring to the error report control circuit 9, and 35 is a time monitoring instruction signal for instructing the time monitoring circuit 8 to start. When the time monitoring circuit 8 is instructed to start time monitoring by the time monitoring instruction signal 41, it is a counter reset signal that instructs to reset the contents of the error occurrence count storage circuit 5. 1. During normal operation of this device Microinstruction data 30 read from control storage device 1 according to address 31 is used to control arithmetic unit 4 via switching circuit 3.

読み出しだデータ30にエラーがあるか否かは、エラー
検出訂正回路2によって判定がなされるとともに、訂正
可能なエラーが検出された場合には、それを報告する検
出信号34により、エラー訂正中に未訂正のデータ30
で演算部4が動作しないようにし、またエラー訂正完了
後その訂正済データ33によって正常に動作が続行され
るように制御を行なう。
Whether or not there is an error in the read data 30 is determined by the error detection and correction circuit 2, and if a correctable error is detected, a detection signal 34 that reports it is used to detect the error during error correction. Uncorrected data 30
Control is performed so that the arithmetic unit 4 does not operate, and after the error correction is completed, the operation is continued normally using the corrected data 33.

訂正可能エラー検出信号34はまた、エラー発生回数記
憶回路50カウントアツプ信号としても使用され、訂正
可能エラー検出信号34が発生すると、エラー発生回数
記憶回路5の内容に1が加算される。
The correctable error detection signal 34 is also used as a count up signal for the error occurrence number storage circuit 50, and when the correctable error detection signal 34 is generated, 1 is added to the contents of the error occurrence number storage circuit 5.

エラースレッショルド回路6には、あらかじめ与えられ
だ値37が初期設定されており、この初期設定値38と
、訂正可能エラー発生回数の値36とが比較回路7によ
り比較され一致すると、比較回路7よシ一致信号39が
発生する。一致信号39が発生すると、エラー報告制御
回路9により、エラー報告が抑止されてい々ければ、エ
ラー報告信号42を発生し、以後のエラー判□告を抑止
するとともに、時間監視指示信号41により、時IH1
監祈回路8に時間監視の指示が行なわれ、エラー報告が
すでに抑止されていれば、一致信号39が発生してもエ
ラー報告信号42は発生を抑止され、時間監視の指示も
行なわれない。
The error threshold circuit 6 is initially set to a value 37 given in advance, and when this initial setting value 38 and the value 36 of the number of correctable error occurrences are compared by the comparator circuit 7 and match, the comparator circuit 7 A match signal 39 is generated. When the coincidence signal 39 is generated, the error report control circuit 9 generates an error report signal 42 as the error report continues to be suppressed, suppressing subsequent error judgments, and using the time monitoring instruction signal 41, Time IH1
If the time monitoring circuit 8 is instructed to monitor the time and error reporting is already suppressed, even if the coincidence signal 39 is generated, the error report signal 42 is suppressed from being generated and no time monitoring instruction is issued.

時間監視回路8は、あらかじめ与えられた値43が初期
設定されておシ、時間監視指示信号41によシ、時間監
視の指示が行なわれるとエラー発生回数記憶回路5の内
容をリセットすることを指示するカウンタリセット信号
35を発生し、以徒一定時間毎に時間監視回路8の値が
1づつ減算されていく。時間監視回路8の値が0に達す
ると、時間監視終了信号40が発生するとともに、時間
監視回路8には、再びあらかじめ与えられた値43が設
定される。
The time monitoring circuit 8 is initially set to a predetermined value 43, and resets the contents of the error occurrence count storage circuit 5 when a time monitoring instruction is given according to the time monitoring instruction signal 41. A counter reset signal 35 is generated to instruct the counter reset signal 35, and thereafter, the value of the time monitoring circuit 8 is subtracted by 1 at fixed time intervals. When the value of the time monitoring circuit 8 reaches 0, a time monitoring end signal 40 is generated and the time monitoring circuit 8 is again set to the predetermined value 43.

エラー報告制御回路9は、時間監視終了信号40が入力
されると訂正可能エラー発生回数の値36を参照し、時
間監視中の訂正可能エラー発生回数の値がOならば、エ
ラー報告の抑止を解除し、訂正可能エラー発生回数の値
が0でなければエラー報告信号42を発生し以後は再び
前記エラー報告信号42の発生を抑止するとともに時間
監視指示信号41によ9時間監視回路8に時間監視の指
示が行なわれる。
When the time monitoring end signal 40 is input, the error report control circuit 9 refers to the value 36 of the number of correctable error occurrences, and if the value of the number of correctable error occurrences during time monitoring is O, suppresses error reporting. If the value of the correctable error occurrence count is 0, an error report signal 42 is generated, and thereafter, the generation of the error report signal 42 is suppressed again, and the time monitoring circuit 8 is notified of the time by the time monitoring instruction signal 41. Monitoring instructions are given.

上記のような構成をとることによυ、本丈施例の装置は
、訂正可能なエラーが報告されると、以後時間監視を実
施してあらかじめ設定された時間内に訂正可能なエラー
が発生しなければ、一時的な障害とみ表し、固定的な障
害との区別をはつきシさせることにより、固定的な障害
であれば、訂正可能々エラー訂正信号の発生を抑止し不
必要なエラーログ情報をとることによる性能借上を防止
し、一時的な障害であれば、続けて、予防保守に必要な
エラーログ情報をとるととにより、よシ保守性、信頼性
の高い装置を実現することができる。
By adopting the above configuration, when a correctable error is reported, the device of this embodiment performs time monitoring to ensure that a correctable error occurs within a preset time. Otherwise, it will be treated as a temporary failure and will be distinguished from a fixed failure.If it is a permanent failure, it will be possible to correct it.The generation of error correction signals will be suppressed and unnecessary error logs will be saved. By preventing performance borrowing by collecting information, and in case of temporary failures, we can continue to collect error log information necessary for preventive maintenance, thereby achieving highly maintainable and reliable equipment. be able to.

〔発明の効果〕〔Effect of the invention〕

本発明には、以上費明したように、訂正■]能なエラー
報告信号発生後は、以後エラー報告信号の発生を抑止す
るとともに時間監視を実施、 シ、監視時間中に訂正可
能なエラーが報告されるかどうかによシ固定的障害と一
時的障害を明石′6に判別できるように構成することに
より、より保守性、信頼性の高い装置を実現できるとい
う効果かある。
As explained above, the present invention has the following features: After the occurrence of a correctable error report signal, the generation of the error report signal is suppressed and time monitoring is performed. By configuring the system so that fixed failures and temporary failures can be clearly distinguished depending on whether they are reported or not, it is possible to realize a device with higher maintainability and reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図である。 FIG. 1 is a block diagram of one embodiment of the present invention.

Claims (1)

【特許請求の範囲】 制御記憶装置にマイクロプログラムをロードし。 該マイクロプログラムを順次読み出してデータ処理を行
なう情報処理装置において、前Bピ制御に憶装置からの
マイクロインストラクション読み出し時に読み出された
マイクロインストラクションデータのエラーを検出する
手段と、検出し7だエラーが訂正可能なエラーであれば
前記データを訂正する手段と、前記エラーの訂正回数と
あらかじめ設定された値とを比較して一致すればエラー
報告信号を発生する手段と、前記エラー報告信号発生後
は前記エラー報告信号の発生を抑止する手段と、あらか
じめ設定された一定時間内に新たなエラーの訂正があれ
ばエラー報告信号を発生してその後は祠び前記エラー報
告信号の発生を抑止する手段と、新たなエラーの訂正が
なければ前記エラー報告信号発生の抑止を解除する手段
とを含むことを特徴とする情報処理装置。
[Claims] Loading a microprogram into a control storage device. In an information processing device that sequentially reads the microprograms and performs data processing, the pre-B pin control includes means for detecting an error in the microinstruction data read when reading the microinstruction from the storage device; means for correcting the data if the error is correctable; means for comparing the number of corrections of the error with a preset value and generating an error report signal if they match; means for suppressing generation of the error report signal; and means for generating an error report signal if a new error is corrected within a preset certain period of time and thereafter suppressing generation of the error report signal; , means for canceling the suppression of generation of the error report signal if no new error is corrected.
JP57164476A 1982-09-21 1982-09-21 Information processing device Granted JPS5953941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57164476A JPS5953941A (en) 1982-09-21 1982-09-21 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57164476A JPS5953941A (en) 1982-09-21 1982-09-21 Information processing device

Publications (2)

Publication Number Publication Date
JPS5953941A true JPS5953941A (en) 1984-03-28
JPH0218506B2 JPH0218506B2 (en) 1990-04-25

Family

ID=15793897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57164476A Granted JPS5953941A (en) 1982-09-21 1982-09-21 Information processing device

Country Status (1)

Country Link
JP (1) JPS5953941A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010170462A (en) * 2009-01-26 2010-08-05 Nec Computertechno Ltd Fault handling device and method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03103306U (en) * 1990-02-13 1991-10-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010170462A (en) * 2009-01-26 2010-08-05 Nec Computertechno Ltd Fault handling device and method

Also Published As

Publication number Publication date
JPH0218506B2 (en) 1990-04-25

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