JPS595668A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high density, to reduce P-N junction capacity, and to obtain a high speed, by breaking a metal at the boundary between an emitter region and a base contact part. CONSTITUTION:A second SiO2 film 30 is formed on a wafer 21, and heat treatment is performed. IMpurities for forming an N type are diffused in a poly Si pattern, and an emitter region 31 is formed. When an Al film 33 is evaporated on the wafer 21 to the thickness of, e.g. about 0.3-1.0mum, the Al film 33 is broken by an eaves part 34 of an second SiO2 film pattern 32. The thickness of the Al evaporated film 33 is set so that it is broken by the thickness of a poly Si film 29 and the amount of side etching. Then, Al wiring patterns 35 and 36 are formed by photoetching technology. At this time, the Al wiring at the eaves part 34 is already broken. Therefore separation of the Al wiring pattern 36 at a base part and the Al wiring pattern 35 at an emitter part can be performed by self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and in particular provides a method of forming metal wiring in a base region and an emitter region in a self-aligned manner in a bipolar semiconductor device.

3 An example of a conventional NPN type bipolar semiconductor device is shown in Figure 1A.
- Show GK. 1A-F are cross-sectional views, and FIG. 1G is a top view.

First, a first S*02 film 2 is formed on an N-type semiconductor substrate 1 (hereinafter referred to as a wafer) by thermal oxidation or CVD, and then a base window region 3 is formed by photoetching, and P-type impurities are heated. After a base region 4 is formed by diffusion by ion implantation or the like, a PolySt film 5 containing N-type impurities is deposited, and then a Si3N4 film 6 is deposited. Thereafter, a photosensitive resin pattern 7 for forming an emitter pattern is formed (FIG. 1A).

Next, using the photosensitive resin pattern 7 as a mask, the Si3N4 film 6 is etched to form a 513N4 pattern 8, and then the Si3N4 film 6 is etched using the Si3N4 pattern 8 as a mask.
The film 5 is etched to form a PolySi pattern 9 (FIG. 1B).

Next, a second SiO2 film 10 is formed on the wafer 1 by thermal oxidation.
Do all 10. At this time, the portion where the 313N4 pattern 8 is formed is not oxidized. Katsutako's special release Elili
59-51E68 (2) By thermal oxidation, the above Po1
The N-type impurity in the y-Si pattern 9 is diffused to form an emitter region 11. After that, a photosensitive resin pattern 12 for forming a base contact is formed (FIG. 1C).
).

Using the photosensitive resin pattern 12 as a mask, the second (
') After etching the S 102 film 10 and forming the base contact 13, the photosensitive resin pattern 12 is removed, and then the S 1 3N4 pattern 8 is removed to form the emitter contact 14 (FIG. 1D). Thereafter, an A° C. film 16 is formed on the wafer 1 (FIG. 1E).

Next, an A2 wiring pattern 16 is formed by photoetching (FIG. 1F, G).

However, in the conventional method, the distance a between the base contact 13 and the emitter region 11 is A! Wiring pattern 16
With a spacing of 13°, the base contact 13° and the emitter region 11
It is determined by the sum of the amount and the amount taking into account misalignment with the Aβ wiring pattern 16. It is determined by photo-etching technology, and is usually 3 to 6 μm.
As the above is required, the distance between the emitter region 11 and the Hajime course contact 13 becomes long, and the resistance between them becomes large, which becomes a very big problem when trying to increase the speed, and also makes it difficult to increase the density. was also a major hindrance.

The present invention has been made in view of the above-mentioned drawbacks, and is characterized in that the distance between the metal wiring between the emitter region and the base contact portion is reduced by disconnecting the metal at the boundary between the emitter region and the base contact portion.

A first embodiment of the method for manufacturing a semiconductor device of the present invention is shown in FIGS. 2A-H. Figures 2A-G are cross-sectional views, and Figure 2H
is a top view.

A first S x O
After forming the two films, a first SIO2 pattern 22 for forming a pace region is formed by photoetching, and a P-type impurity is introduced by thermal diffusion or ion implantation to form a base region 23. After that, a second 8102 pattern 24 is formed in a part of the base region 23 (FIG. 2A)
.

Next, a Po1ySi film 26 containing N-type impurities is deposited to a thickness of about 0.2 to 0.5 μm on the wafer 21, and the Si
After depositing the 3N4 film 26 to a thickness of about 0.06 to 0.2 .mu.m, a photosensitive resin pattern 27 for forming an emitter and an emitter contact is formed (FIG. 2B).

After that, using the photosensitive resin pattern 27 as a mask,
Etching the i3N4 film 46 to form a 313N4 film pattern 2
After forming Po1y 5 using pattern 28 as a mask,
PolySi pattern 29 is formed by etching i26. At this time, etching 26 is performed by isotropic etching such as wet etching, and this side etching amount β
For example, about 0.3 to 1.0 μm, and S
s The 3N4 pattern 28 is formed into a canopy shape (FIG. 2C).

Next, a second 8102 film 3 is deposited on the wafer 21 by the CVD method.
At the same time as forming Po1yS, heat treatment is performed to form PolyS
An emitter region 31 is formed by diffusing the N-type forming impurity in the i-pattern (FIG. 2D).

Thereafter, the entire second Sio2 film 3o is etched by an anisotropic etching method such as reactive sputter etching or sputter etching 7.
y side tTl of Si pattern 29 2nd S i O2
After leaving the film pattern 32, Si3N4 Bakun 28
(Fig. 2E).

The vCAR film 33 on the wafer 21 has a thickness of, for example, 0.3-1.0μ.
After m deposition, the A2 film 33 is disconnected at the canopy portion 34 of the second S102 film pattern 32. The thickness of the Aβ film 33 to be deposited is set so as to cause disconnection depending on the thickness of the PolySt 29 and the amount of side etching (FIG. 2F).

Next, the An wiring pattern 35.
form 36. At this time, the Al wiring in the eaves part 34 has already been disconnected, so the A! The wiring pattern 36 and the second wiring pattern 35 in the emitter section can be separated by self-alignment (FIG. 2G).

A second embodiment of the method for manufacturing a semiconductor device of the present invention is shown in FIGS. 3A-H.

First, a first S x 02 is placed on an N-type silicon wafer 41.
After forming the film, a first SiO2 pattern 42 for forming the base region is formed using photoetching technology, and P-type impurities are introduced using thermal diffusion or ion implantation to form the base region. Form 43. Thereafter, a second SiO2 pattern 44 is deposited on a part of the base region 43. Next, a PolySt film 45 containing an N-type forming impurity is deposited to a thickness of about 0.2-0.5 pm on the wafer 41, and Si3N4 is deposited on a part of the base region 43. After depositing the film 46 to a thickness of about 0.05 to 0.2 μm, a photosensitive resin pattern 47 for forming an emitter and an emitter contact is formed (FIG. 3B).

Mask the photosensitive resin pattern 47 with the Si3N4 film 4.
After etching 6 and forming Si3N4 pattern 4B,
3N4 pattern 48? As a step, the PolySi film 45 is etched to form a PolySi pattern 49.

At this time, the PolySt film 45 is etched by isotropic etching such as wet etching, and the side etching amount β is set to, for example, about 0.3 to 1.0 μm, so that the Si3N4 pattern 48 becomes an eaves shape. form (Figure 3C).

Next, the Si3N4 film pattern 48 is applied to the base region 43.
Using as a mask, P-type impurities are introduced by ion implantation to form a graft base region 50 (FIG. 3D).
.

Thereafter, a second SiO layer is applied to the wafer 41'' by a CVD method.
□The film 61 is completely coated and heat treated to remove the above Po.
The N-type forming impurity in the 1y St pattern 49 is diffused to form an emitter region 52 (FIG. 3E).

Next, the entire second Si○2 film 61 is etched by an anisotropic etching method such as reactive sputter etching or sputter etching to form a PolySi pattern 4.
After forming the second SzO2 film pattern 53 on the side surface of the Si3N4 pattern 48 (FIG. 3F).

The Aμ film 64 is formed on the wafer 41 to a thickness of, for example, 0.3 to 1.0 μm.
When the second 8102 film pattern 53 is evaporated, the Aλ film 64 is disconnected at the eaves portion 66 of the second 8102 film pattern 53. A2 film 64 to be deposited
The film thickness is set so as to cause disconnection depending on the film thickness of PolySi 49 and the side etching amount l (3rd
Figure G).

Next, the Al wiring pattern 56 was formed using photoetching technology.
．． form 57. At this time, since the Al wiring has already been disconnected in the eaves part 66, the Al wiring pattern 67 in the base part can be separated from the Al wiring pattern 66 in the emitter part by self-alignment (Fig. 3H).
.

As described above, with the method of the present invention, when a metal film for wiring is deposited, since the emitter part and the base part are separated by a disconnection, it is necessary to consider the margin for photoetching by considering only the side etching amount e. High density can be achieved without red color. In addition, by making the distance between the emitter region and the metal wiring in the base extremely small, the emitter
Since the resistance between the bases can be reduced and the size of the transistor can be reduced, the PN junction capacitance can be reduced and the speed can be increased. Further, if the graft base is made in a self-aligning manner as in the second embodiment and the resistance is further reduced, 11· and -2 are also possible. Furthermore, since Al is placed on the PolySi, the wiring resistance in the emitter region can also be reduced.

Although this embodiment describes an NPN type semiconductor device,
The same applies to PNP type semiconductor devices, and can also be used for diodes, resistors, etc.

Although anisotropic etching has been described as a method for leaving the SIO2 film on the side surfaces, it goes without saying that other methods may be used as long as the 5IO2 film can be left on the side surfaces. Although Si3N4 is used as the film on the PolySi in this embodiment, it does not have to be an insulating film, but may be any film that can serve as a mask in PolySt etching.

As described above, with the method of the present invention, the metal films in the base region and emitter region can be separated in a self-aligned manner during vapor deposition, so fine separation is possible regardless of photoetching technology. It has great industrial value as it allows for high-density and high-speed integrated circuits.

[Brief explanation of the drawing]

12.3. - Special aperture a 59-5668 (4) Figure 1A-F is a cross-sectional view of the manufacturing process of a conventional bipolar semiconductor device, Figure 1G is a schematic plan pattern diagram of the main part of the same F, Figure 2A-G , and FIGS. 3A-3H are sectional views showing the manufacturing process of a bipolar semiconductor device according to an embodiment of the present invention. 3A to 3H show a second embodiment of the method for manufacturing a semiconductor device of the present invention. 21.41...N-type St wafer, 23.43...
...Pace area, 29, 49...Poly
St pattern, 28.48...813N4 pattern, 31.52...river/emitter region, 32.63...
...Third 8102 pattern, 35.36.56.
...Al wiring pattern. Name of agent: Patent attorney Toshio Nakao and one other person
1 Figure 1 Figure 1 ζ 32 Figure 4 23 31 23 31 艷 3 Figure 1 Δ Figure 3 δθ 4344 6θ 4362 44 3rd rlA. 3 60 4362 44

Claims (2)

[Claims] (1) Forming a first conductive film containing impurities of one conductivity type on a semiconductor substrate, and forming a second film on the first film.
a step of forming a predetermined second film pattern, etching the first film using the second film pattern as a mask, and etching a predetermined film pattern from the edge of the second film pattern. forming the first film pattern so as to extend inward by the length; and forming a second film pattern on the side of the first film pattern and the side in contact with the first film and from which the first film has been removed. forming a first insulating film on the film pattern portion;
A method for manufacturing a semiconductor device, comprising the steps of removing the second film pattern, and forming a separate thin film for conductor wiring on the semiconductor substrate and the first film pattern. (2) forming a conductive first film containing impurities of one conductivity type on the semiconductor substrate; and forming a second film on the first film.
a step of forming a predetermined second film pattern, etching the first film using the second film pattern as a mask, and etching a predetermined film pattern from the edge of the second film pattern. forming the first film pattern so as to extend inward by the length; and using the first film pattern as a mask, introducing an opposite conductivity type impurity into a predetermined region of the semiconductor substrate by ion implantation; forming a first insulating film on a side surface of the first film pattern and a second film pattern portion on a side in contact with the first film and from which the first film has been removed; a step of removing the film pattern;
A method for manufacturing a semiconductor device, comprising the step of forming a thin film for conductor wiring on the semiconductor substrate and the first film pattern.