JPS5961940A - Bonding method of semiconductor chip - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field to which the invention relates The present invention relates to a method of bonding a semiconductor chip such as an LSI (large scale integrated circuit i+!8) and a lead frame or a substrate.

(1)) Prior art and its drawbacks Conventionally, in order to bond a semiconductor chip and a lead frame or a substrate, a bump portion is formed on either the substrate or the lead frame, or on the semiconductor chip, and the bump portion is heated and melted. I'm letting it happen. For example, as shown in Figure 1, half 317 chips 1'' and A I? +Cr.

Cu is laminated in this order by vacuum evaporation, and finally Au is plated 1xU (Jb) to form bump electrodes 2.

This is shown in Figure 2 (a), (+)).
The bump electrode 2 is brought into contact with a non-electrical part of the plated lead frame 3 or substrate 4 and heated to about 270°C. By this heating, the bump electrode 2 is heated to the lead frame 3.
Alternatively, the so-called inner lead bonding method is used when molding with epoxy resin or the like to form a single LSI bank board. , (+)) Figure is Calculator 9
All clip-deep bonding methods used in hybrid ICs for mounting watches, cameras, etc. are shown.

However, these bonding methods result in the formation of insulating products within the knob electrode that leaks out the bump electrode 2 at the stage of mounting it as an LSi or hybrid IC, i<1≦ product. There were some inconveniences. The cause of this is 1) Buff City (as mentioned in 1)
・;When forming J42, it is heated to about 270'C to alloy it, but there is a rjJ ability of 11 It is from. Furthermore, this means that even after mounting, the one-control property of the cumulative r is lower than the melting point of the alloy layer of the bump electrode, which may have the disadvantage of poor thermal stability during use. Ta.

Other conventional methods of positing include the conductive elbow gluing method and the 11f springing method. This is half no j',
'[Ni, Au, etc. are coated on the body by coating or vacuum deposition, and mainly A! / + η containing fine powder such as Au ￥ Conductor bag-7 with conductive ebogishi branch 1 fat
This is a method of layering it on the surface.

1~ However, this method uses epoxy (Yellow Body Paint 14
1 is low at around 150″C, so compared to the above method, the
11. It is more difficult to imitate the surface of the heat-reduced grain, and since it is difficult to etch the grain, it has the disadvantage of lacking compatibility when mass-produced.

(c) Purpose of the Invention This invention solves the following two drawbacks. Minasano 1. It is suitable for mass production, and is suitable for semiconductor depths and lead frames or substrates 1-4-. An object of the present invention is to provide a method for bonding semiconductor chips that improves the heat resistance of bonding 81≦1.

(cl) Structure of the Invention To summarize the entire invention, a polyimide resin in which non-electrical powder is dispersed is applied, followed by heating and etching treatment to form all non-electrical resin bumps in a desired pattern, and quissing is performed. It is characterized in that the bump portion between the semiconductor depth and the lead frame or substrate is bonded by secondary heating.

(e) Description of Embodiments A method for forming bumps by photo-etching will be described with reference to FIG. In the same figure (a), a semiconductor phenol with a circuit pattern formed thereon is shown.
Apply the polyimide solution containing all the powder using a spinner, roll stamp 111, etc.
A film portion) 22 is formed. Next, polyimide r, (1//
, or L-) value 1 fat-7-1・22 'K l 20
-C degree V This linear addition: p (t, polyimide melt t (k
The solution is evaporated (filtered) and imidized to a semi-hardened state.

Then, as shown in (1) 1121, remove the part that should become the VtC bag part and remove the force by applying the raw photoresis l-5 case screen IEIJ jill '9 K. This can be treated with a corsodine compound consisting of ethylenediamine and hydrazino or other known enzymatic compounds.
When the edge sifting process is performed on the palm 1, the resin coat 22 (polyimide layer) in the area where the bottom resist 5 is not formed is removed, as shown in FIG. 1C.

When the potresist 5 is removed, the resin coating 22 is left only on the desired part of the F-body wafer 11 as shown in FIG. When it is divided into many parts, one half j (γ body chinonol becomes Isu 1 (e), and the remaining (k1 fat coat 22 becomes buff 1η/J2).

Screen mark 1+ill tjH bag +
Formation method/1: will be explained. This method is the same as the above-mentioned poten-fsik method (2).
Apply a screen or metal mask to the desired part of the pattern shape 1 on the semiconductor square or 11 soil, and form A with 6 as shown in Figure 4.
y of the polyimide solution containing all 11 parts of the powder (111 fingers! 22). And photo etching θ in the same way as this time (☆ 1 Heat the fat coat 22 to evaporate the agent. The semiconductor wafer 11 is made into a semi-hardened state.Next, a large number of semiconductor depths 1 are formed by glazing the semiconductor wafer 11.

Here, the polyimide resin in which the proprietary powder used in this example is dispersed will be explained.

As a resin, polyamic acid dimylylacetate!・Amide (DMAC) and N-methyl-2-pyrrolidone (NMP)
, dimethylborumamide (DM F ), or the like is used. A fine powder of Ay was mixed into this solution at a ratio of 40%, and the electrical conductivity of the solution was set to 4-4 J/.

When the above solution is heated to about 120° C., the solvent in the solution evaporates, some of the resin evaporates, and the polyamic acid is imidized. When this is heated, the resin becomes semi-hardened.
It becomes an island and loses its slate quality. At this time, the resin reaction has almost stopped! '' and is extremely easy to handle. In other words, the reaction progresses extremely slowly in a room atmosphere, and it is possible to use an official seal for long-term storage. Therefore, in this semi-cured state, the steps shown in FIG. 3, 4b) to 4e, or the step shown in FIG. 4 are performed. This semi-cured resin, in which the reaction has stopped, can be further heated to cause the reaction to proceed and regain its tackiness. As will be described later, the adhesion caused by this heating makes it possible to bond between the depth and the substrate or lead frame via the bump portion 2.

The solution that is imidized to become a resin is not limited to those mentioned above, but can be any solution that is generally classified as a polyimide resin, and these can be used in the same process as above. And, the conductive fine powder is not limited to Ay, but may also be Au.

Next, a method for bonding the semiconductor chip 1 and the lead frame 3 or substrate 4 by secondary heating the bump portions 2 will be described.

FIG. 5 is a diagram showing the state of bonding work between the semiconductor depth 1 and the lead frame 3 by the inner lead bonding method. For bonding, place the lead frame 3 to be bonded on the bump portion 2 of the semiconductor chip 1'', and then
This is done by slightly applying pressure using a heater chip 6 heated to about .degree.

The time required for this joining is several seconds.

FIG. 6 is a diagram showing the state of bonding work between the semiconductor chip 1 and the substrate 4 by the clip chip bonding method.

A die collector door operated by a microcomputer-controlled manipulator (not shown) holds the semiconductor dip 1 under negative pressure at the suction port 8, and places it on a desired portion of the substrate 4 as shown in the figure. 250° from the bottom of the board 4 as indicated by the arrow.
The bump portion 2 is hardened to the bottom of the substrate 4 by heating to about C.

As described above, the bump portion 2 in the semi-cured set was heated to 250°C.
If secondary heating is performed to a certain degree, the TTRJ resin will start reacting again, and adhesive bonding will be performed between the chip and the lead frame or between the chip and the substrate. The reason why a slight pressure is applied by the heater chip 6-1 or the die collet 7 is to ensure sufficient adhesive bonding.

The above has described the bonding process when the bump portions 2 are formed on the semi-3Hp chip 1.Next, we will discuss the case where the bump portions 2 called petestals are formed on the substrate 4 and the semiconductor depth and the substrate are bonded. I will explain. FIG. 7 is a diagram showing a state in which a bump portion 2 called a petestal is formed on the substrate 4 side by the same method as described above, and a semiconductor chip 1 on which all electrodes of Al are formed is bonded to the bonding portion. The bonding method is almost the same as in the above two examples, and the only difference is that the bump portion is formed on the substrate 2 and is defective. Therefore, /M'
It is possible to move the electrode part as shown by the arrow, place it on the bump part 2, apply a slight pressure, and further heat the bump part 2 to about 250°C to perform the bonding. Thus, the bump portion of the embodiment of the present invention can be subjected to the ζ-coupling process in several λ by heating to about 250'C (preferably by further applying a slight pressure). Once bonded, the thermal stability is extremely good. Even if the temperature of the solder rises above 250°C through some kind of heat treatment when it becomes a product, that heat only further advances the bonding action and increases the stability. As a result, the final temperature of the bump portion 2 is 400 DEG C. or higher, and it is possible to achieve a -1-1 thermal stability that ensures excellent mass productivity.

(f) Effects of the Invention As described above, according to the semiconductor chip bonding method of the present invention, the heat resistance of the bump electrode at the bonding portion is improved because the polyimide resin has a very high 1liiJ heat resistance.

As a result, heat treatment such as half-cutting of the completed device becomes easy, the work of mounting it on an electronic circuit or the like is greatly simplified, and the life of the completed device itself is extended. Furthermore, since a polyimide resin which becomes semi-cured by 1 inch with a reactive edge secured through subsequent addition is used, etching can be completely performed at the semi-cured stage.

Etching can be carried out at the final stage, which has the advantage of greatly improving mass production.

[Brief explanation of drawings]

Fig. 1 is a sectional view of a conventional bump electrode, Fig. 2 is a diagram showing the bonding state of a conventional bump electrode, and Fig. 3 is a process for forming a υ bump electrode by a photoetching method.
II'J VrC IXI, Figure 4 is screen mark 1
A diagram explaining the method of forming a passivation electrode using the +ILJ method, Section 5 is a diagram showing the state in which semiconductor chips and lead frames are bonded using the inner lead bonding method, and FIG. FIG. 7 is a diagram illustrating the entire process for bonding the substrates together, and FIG. 7 is a diagram showing the process for bonding the half-sized 17-piece chimp and base plate using the flip dizzo bonding method when a pedestal is formed on the substrate. 1. Semiconductor chip, 2゛ bump (bump electrode, pedestal), 3.° lead frame, 4.
22.Resin coat. Applicant Sharp Corporation Agent Patent Attorney Hisao Komori Figure 1 Figure 5 Figure 6 f...? +;, Hi,
Figure 7 Figure 3 Figure 41/CI

Claims (1)

[Claims] (1) Apply polyimide +-FF+ fat containing 3RP commercial powder dispersed and mixed with molten resin onto either the substrate, lead frame, or semiconductor surface, and heat it to a semi-hardened state. ('r! A thin fat film is formed, and the desired conductivity is achieved by V-etching.) A keratin basive part is formed, and then the pap part is placed between the diced semiconductor chip and the lead frame or substrate. A method for bonding semiconductor chips, characterized in that the bonding is performed using only one force.