JPS5962960A - Data transfer circuit of computer - Google Patents

Abstract

PURPOSE:To make data transfer possible without intervention of computers and without holding them by connecting directly memory address drivers and memory data drivers on both computer sides to each other respectively and providing a transfer switching controller. CONSTITUTION:The start address is designated by an address register 29. The number of data to be transferred is set to a counter 30, and data drivers 17 and 18 are set by a read/write set means 27. A switching means 26 is switched to the transfer mode, and computers 11, 12 and memories 19, 20 are disconnected, and memories 19 and 20 are connected directly by directly connecting lines l1 and l2. Each time a timing circuit generates a timing clock, data in the memory 19 is transferred to the memory 20 through the line l2 successively from the start address. This transfer is continued until the counter 30 generates a count end signal. When the transfer is completed, an interrupt signal is applied from the switching means 26 to computers 11 and 12, and memories are connected to computers 11 and 12 again.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides at least two -T knobs 1--T11.
11 relates to a data transfer circuit for transferring data stored in the memory of the computer computer of -110 to the memory of the computer of computer 110;

As this type of data transfer circuit, ijc t r, l first
The circuits shown in Figures (A) and (B) were commonly used1.
, 1 out of 1 1.2 is combination j-1'3. 4): j: Memory, 5, 6 (d'/real or parallel data transfer r>
Fino interface, 7.81d system bus interface, 9 is a system bus.

In the conventional circuit of figure (A) at around 7, the computer 1.2
The point is that the computer 1.2 is unable to perform any other work since it intervenes between the memory 3.4 and the interface 5.6 to perform all data transfers. I) M A transfer (direct memory °
Access) also has the same disadvantage as above, in that the computer is forced to go into standby mode while data is being transferred. -n, Figure (B1) also has the same drawbacks as the conventional circuit described in l-, as the computer 2 does not enter the standby state when data is transferred from the convenience store 1 to the memory 4 of the computer 2. (also).

The present invention solves these drawbacks by providing a novel data transfer circuit that can transfer data from memory to IU directly without intervening a C, C computer or making it standby; C47).

I'll et al.1. The 1-to-1 transfer circuit of the computer computer according to the invention includes at least two computers, an address decoder attached to or built in each computer, an address decoder, a memory address driver, a memory data driver, and a memory. The memory address drivers and the memory data drivers are directly connected to each other, and at least one switching controller is provided for transferring data in one memory to the other memory through the 1U connection line. The transfer switching controller transfers data through all lines directly connected to the memory address driver and the redata driver.
The section means to switch to a possible transfer mode and the 1111th memory data driver entering the booter 1, output L7
In addition, there is a read/write setting means for setting the 11110 memory data drivers to receive data, a timing clock l'6 in the transfer mode, and a transfer 1. z′1 of the data to be
An address decoder that specifies the starting address, and a +'f: l
-1: The number of data to be set is set to 7, and when the timing clock is counted by the set number of data, the count ends r (it has a counter that emits the words 7 and 7).
Every time the 4677 circuit lights up the timing clock -)
The data in the memory of j is transferred to the first number [sequentially from 1] to 11 of j specified by the address register, and when the counter issues the count end signal 4, The feature is that it is configured to complete the transposition.

1. An embodiment of the present invention is described below based on FIG. 2.

I will clarify. The diagram shows -1 on the /1 side from the chain line in the center: / View from the memory of 11 to the right A1!
The amount of data transferred is 18 times more! 1 each, each = I input footer II, +2 is approximately address data 1-data 13, 14, memory address driver 15゜16
, meter r'-ta driver 17.18 and memory 1q,
It is equipped with 211 attached or built-in. Address decoders 13 and 14 are connected to memories 19 and 2 (
Which address should I assign to 5-m-7-' or between
The characters are missing and are connected to the address buses 21 and 22 of the computer 11°1z.

Memory address driver 15. The 15 wise words from 13.14 are here:
+1 'Y' ((7) Works hard to specify all addresses. No 1 = resort driver 17. IRIr: t data This is to extract 6 children from all memory, Data bus 2 of 1 and 12: 1 and memory 19.ZOl+, which are also connected to 1 and 24, for example
Two memories are used.

++1;i, although not shown, each computer I+,
+2 is tangent to the memory of the number of ponds in addition to the 110th memo 1J19, 211.

Memory address driver 15. of both computers 1], 121111. l(i to each other and me esujl-
The controller drivers 17 and 18 are connected to each other on lines l+ and /2, and the command of the transfer switching controller 25 that was installed on the left side of the combination I and I was set. The data in memory 19 of node j is transferred to the memory 20 of other node j through this direct twin connection. Transfer command pregnant i now transfer J, q
lJ, I;, ・li′=jnl−n−ra25 is,
Suj' Late Senju 1mo 26, +'flf+ [7-1141
27, timing circuit 28,
7” from dress register z9 and counter 30) Hr
H is made.

The switching means 26 is the memory address driver 15. IG, memory data driver 17. ll'l' (5-turn, switch to ku mode, for example, a flip-flop is used. Transfer mode is changed here, memory address driver 1
5.16, memory data driver 17, I8 and computer 11.12 are disconnected. Therefore, in this state of deafness (rl two memories 19.2++ are connected directly to computer 11, 125f without intervention)
+, l*, and data is transferred through this line as 'I fit: h. Ten thousand,
In this transfer mode, each computer 11, 121'j is disconnected from the transfer memories 1q, z+1, so
It is possible to perform the funeral using other memory (not shown).

The reading/writing setting means 271d having 27 setting means 1111 is referred to as the F master side. 1. When sending data from the memory data driver 17i in the master 1ull, the setting means 27' (((hereinafter referred to as slave (1111)) reads the memory data driver 17i in the master 1ull. set 17
, Master 11111 When receiving money, it is set in the opposite way, for example, a flip-flop is used.

The timing circuit 28 generates a timing clock at a certain frequency, and is constituted by a general lock pulse generator. This circuit 2 R(ri rift 'r4+
F. The Lu1l switching means 26 is activated when switched to the transfer mode, and is stopped when the counter 30 completes counting. When the timing circuit is in operation, the timing clock it emits is sent to the memory address driver 15.1.
6. Memory data driver 17. The data added to ll'l and stored in the memory 19 are sequentially transferred to the memory 2.

In this case, the speed at which all data is transferred is determined by the frequency of the i timing clock (1-). The 7° address register 291. can perform faster transfer by increasing its frequency with the 7° address register 291. This is for specifying all the starting addresses of the data to be transferred. If you are trying to transfer all the data stored in the number 1111 from a certain address in the memory 19, what should I do? It is J)'s turn to define 4.

The counter 30 receives the number of data to be transferred, and the counter 31
i yo IJ countdown, ttij address t/jista 2! The I-j count end signal is sent and the next memory address is specified. Then C, timing 11 for the number of data
When counting, the count end r signal is emitted.

At the end of this count
28 and 1-11 alternate f-stage 21i. The transfer mode is determined by the timing circuit 21 ([1q, as described above, starts and stops according to the count end r signal. U1 change means 26 selects the count end r signal)
Regular Mo Shiroko costs 1M.

Then, the transfer information 1111 is sent from the switching means 26 to the computer 1 (transfer complete). Over the past month, memory 19.20 has been connected to computers 11 and 12.

According to the BL configuration, "address register 291"
After specifying the 5th address and setting the number of data to be transferred in the counter 30, the data driver 1 is set to 17°18'J by the readout pad cent 10 stage 27, and the switching means 2fi'iiz is set. , "Switched to 1 mode, the legal system between computer 11.12 and memory 19.20 was severed, and memory 19 and 211 were directly connected. I!2
The data in the memory 19 is sequentially transferred from the first address to the memory 2 () of the memory 7j through the direct connection line 12 to the IW which issues a timing lock at the timing cycle 1. This turn! When the counter 3 () stops counting, the needle reaches its tip at the moment when the signal is emitted, and on the 19th floor, when the count end signal is issued, the counter 3 () transfers to 1 (7'Ci' - 7'Ci' - 7'Ci' - full rotation iη') 1) If the C1 transfer is completed, a signal is applied to the computer 11.12 from the switching means 26 to j%'ll, and then vt +lT and memory 19.
20 is the core computer 11, 12 + 4Y%i.

Note that on the downstream side 1+t, the throat of the computer 11 is i.
5- Data transfer initiative <'ta There is also one gold, so-called 17 formula in which the master 11111 and the slave side are fixed numbers, but in many cases, the master 1 rule and slave control 11 are i"J '& One thing is hopeful.When n7 change i is rubbed, 11.I 1.:ii self' fire 1 to the example structure 1 is the following times 1g '5 (additional deviation shi, 1: good. 1111
1 to ζ feed switching controller 25 are connected to the computer 12.
All signals between memories are replaced with one 3-state logic circuit, and a master/slave flip-flop is added. Then, only the transfer switching controller z5 on the master side and the signals on the master side are made valid, and those of the slave (1111) are made invalid.

In addition, in addition to the circuits mentioned above, the master side and slave full
If a conversation register is provided between slave 7' (til
The transfer request from 1 becomes 6J ROHI, and it is extremely convenient to be able to determine whether the memory is connected to the computer or is being transferred, and to synchronize the master/slave switching timing. be.

Since the data transfer cycle of the computer according to the present invention is configured as described above, it has the following advantages.

(1) Data can be transferred with the memory fully connected directly without the intervention of a computer, so
None of the computers will have to wait for a long time during the rotation. Therefore, the computer can do other work, and the processing speed of the system as a whole increases.

(The data transfer can be performed at the IN-to-1-'1 timing using the timing clock determined by timing apposition, so by increasing the frequency of the quimic clock regardless of the timing of the computer itself, the large amount of data k it% can be transferred. It is possible to transfer data at high speed.

[Brief explanation of the drawing]

Figure 1 (A) (8) is the conventional 1-way transfer! 116
FIG. 2 is a block diagram showing a data transfer circuit as an example of an embodiment of the present invention. 11.12... Computer name, l: Thought, 14... Address decoder, 15, 1 (i... Meshiri γ address driver, 1-7.18... Memory data driver, 19
．． 20...Memory, 25...Transformation 4I + replacement controller, 26-GIJ replacement means, 27 Readout, douchi set, 1 Fig. 1 (A) = (B)

Claims (1)

[Claims] at least two computers, each computer having a built-in address decoder, a memory address driver, a memory data driver, and a memory;
The memory address drivers and memory data drivers of both computers are directly connected to each other, and at least one transfer device is used to transfer data in one memory to the other memory through a 1U connection link. Switching: l
The controller is equipped with a transfer switch.
The r+-ra is used for data transfer through all direct connection lines of the previous memory driver and memory data driver.
a switching means for switching to a transfer mode capable of transferring data, a memory data driver on the data sending side for reading, a memory data driver for receiving data (a memory data driver for reading data), and a writing setting means for setting the memory data driver on the data sending side to full writing; a timing circuit that issues a timing clock in transfer mode;
/, i L, I: The address register that specifies the number of data to be processed, the number of data to be transposed, and the number of data to be transposed are set, and the timing clock is counted by the set number of data. The counter has a counter that issues a count end signal when the timing clock is triggered, and each time the timing clock is activated, the data in the memory of -)j is sequentially read from the first address specified by the address register.
Transfer to memory of j1. 1) A data transfer circuit for a computer computer, characterized in that the data transfer circuit is configured to complete the transfer when the counter issues a count end signal.