JPH0357055A - Dma transfer control system - Google Patents

Abstract

PURPOSE:To perform DMA (direct memory access) transfer at a high speed by allowing the read bus cycle and the write bus cycle to overlap even in the case of two-bus cycle transfer. CONSTITUTION:A bus cycle start signal BCYST is divided to a bus cycle start signal MBYST 13 for a main storage part (memory) 4 and a bus cycle start signal IBCYST 15 for an input/output device (IO) 2. A bus cycle extending signal IEADY is divided to a bus cycle extending signal IREADY 16 for the memory 4. The read bus cycle and the write bus cycle overlap even in the case of two-bus cycle transfer in this manner. Thus, DMA transfer is performed at t high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to direct memory access (hereinafter referred to as DMAt) of an input/output device in an information processing system.
(transfer) device.

[Conventional technology]

A DMA transfer device uses a common data transfer path (
input/output to increase response time when connected to a system bus (hereinafter referred to as a system bus). ! This is to perform high-speed data transfer between the computer and the main storage device (hereinafter referred to as memory) in place of the central processing unit (hereinafter referred to as CPU). One DMA transfer device can control a plurality of 10 devices, and a DMA transfer path by one IO device is called a channel.

As the performance of the CPU improves, the system bus connected to the CPU becomes faster as the unit time required for one read/write (hereinafter referred to as a bus cycle) becomes shorter.

The width of the remaining system buses is also increasing, and currently there are 32
Many have a bus width of one bit.

However, the transfer speed of the 10 devices is lower than that of the CPU Vc, and most devices have a data transfer width (hereinafter referred to as a boat width) of 8 bits, 16 bits, which is conventional. For this reason, a structure having an IO bus separate from the system bus, or a structure in which a buffer memory IJf is provided and ten devices are connected to the system bus via this buffer memory is being considered. However, providing an IO bus and a buffer memory will lead to cost savings, so here we will consider increasing the speed by creating a configuration in which IO devices are directly connected to the Sosnam bus.

In the conventional [)MAC, transfer methods such as fly-by transfer and two-bus cycle transfer are used.

In the flywheel transfer, reading from the IO device and writing to the memory are performed in one bus cycle, and similarly, reading from the memory and writing to the IO device are performed in one bus cycle. Although this two-by-bye transfer allows high-speed DMA transfer, it has the disadvantage that if the boat width is 2 bytes (16 bits) or more, transfer to an assigned address (odd address) cannot be performed.

On the other hand, 2-bus cycle transfer is a method in which one DMA transfer is performed in two bus cycles, a read bus cycle and a write bus cycle, and it is possible to transfer to a misaligned address, but the transfer requires The disadvantage is that it takes a lot of time.

This will be explained in detail using drawings.

FIG. 5 is a block diagram showing a system S of a conventional direct memory access controller (hereinafter referred to as DMAC), and FIG. 6 is a timing chart when the DMAC of FIG. 5 is operated.

When the IO device 2a becomes ready to read and write data,
DM person transfer request signal (L) RQ for MAC l a
) 17 to activate to initiate a DMA transfer bus cycle. DMACla receives DQ17 and requests the CPU to activate the bus hold request signal and occupy the system bus.

DMACla starts a DMA transfer bus cycle t-R when the bus occupancy permission signal from the CPU becomes active.

Regarding the transfer direction, write transfer is defined as a transfer from the IO% location to the memory, and read transfer is defined as transfer from the memory to the IO device.

In a two-bus cycle transfer, a read bus cycle is started first. BeY8T first in read bus cycle
Activate signal 2l and ADDR, 几/W, M/IO
Each signal 11 is output.

In the case of read transfer, ADDH outputs the address to be read from the memory 4a, and outputs R/W=1 and M/IO=1. Next, when the EADY signal 22 becomes active, the data read from the memory 4a and output to the data bus 12 is written into the internal register of the DMAC 1a.

In the case of write transfer, the boat address of the IO device 2a is output to ADD, and R/W=1 and M/IO=O are output. Next, when the I-LEADY signal 22 becomes active, the data read from the IO device 2a and output to the data bus 12 is written into the internal register of the DMAC la.

After the read bus cycle ends, a write bus cycle is started. In a write bus cycle, BCYS is first
Activate T signal 2l, ADDR, R/W, M
/IO signals 11 are output.

In the case of read transfer, the boat address of the IO device is output to ADDR, and R/W=0 and M/IO=O are output. Next, when the READY signal 22 becomes active, in a read cycle it reads from the internal register of DMACla, outputs it to bus l2, and writes IOf::02aK... In the case of a write transfer, ADDR contains the address to be read from the memory. Outputs k/W=1, M/IO=1. Next, when the Rh, ADY signal 22 becomes active, the data written in the internal register of DMACia in the read cycle is read from the internal register of DMACia and is output to the bus 2 and written to the memory 4aVC.

When the BCYST signal 2l becomes active, the IO device 2a activates the system path color λD D f{, , M/I
(The J, R/W signal 11 is taken in, and the operation starts when AIJDR matches the boat address of the IO device and M/lO=o. 1t/w=1 and @IO device il2a color data are output and output 12K of the system bus path.I
When {,/W=O, data is taken from the system bus 12 and written into the IO device 2a.

When the BCY8T signal 21 of the main memory device 4a becomes active, the M/TO and it/W signals 11 are sent from the system bus.
is taken in and starts operation when M/IO=1. a
,"When w=1, data is read from the address specified by ADDR in the memory 4a and output to bus l2 of the system bus.

When K/W=Q, data is taken from bus 12 of the system bus and written to the address specified by Af)L)R in the memo IJda. FIG. 6 is a diagram showing the timing at this time. When the button in this figure is pressed to start DMA transfer, first, a read bus cycle tR is started. Lead
In the bus cycle, data f is sent from IO device 1 or memory.
{, Read Dl l) Write to internal register of MAC1a.

A write bus cycle is then initiated. Fi in write bus cycle DMAC in 1,1-de bus cycle
The data WD written in the internal register of la is output and written to the memory IJt or IO device.

It can be seen that the read bus cycle and write bus cycle are completely independent in this way, and that twice as many bus cycles are required as compared to fly-by transfer in which reading and writing can be performed in one bus cycle.

[Problem to be solved by the invention]

As mentioned above, regarding the prior art. The disadvantage is that the bus width of the system path and the port width of the IO device are widened, and that when two bus cycle transfers are used to transfer bis-aligned data, the transfer speed becomes significantly slower than fly-by transfers. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA transfer control system that eliminates these drawbacks and allows two bus cycle transfers to be performed without increasing the bus cycle time.

[Means to solve the problem]

The structure of the DMA transfer control method of the present invention includes a DMA transfer device that performs one unit of DMA transfer in two bus cycles: a bus cycle for reading and a bus cycle for writing;
An IO device that connects an IO bus cycle start signal supplied from this DMA transfer device and an IO bus cycle end signal supplied to this D to IA transfer device, and a memory bus cycle end signal supplied to this IO device. and said DM
A main memory device that connects the memory bus cycle start signal supplied from the A transfer device, and an address bus button and a data bus that are commonly connected to each of these devices, and the IO device to the main memory device In the case of DMA transfer, before the memory bus cycle end signal indicates the end of the bus cycle, the IO bus cycle start signal is set to indicate the start of the bus cycle, and the IO address is output to the address bus; At the same time, when the memory bus cycle end signal indicates the end of the bus cycle, the DM
The data that has been temporarily stored in the transfer device A is output to the data bus, and then the memory bus cycle start signal is sent to start the bus cycle before the IO bus cycle end signal indicates the end of the bus cycle. A memory address is output to the address bus as shown in FIG. DM from the device to the IO device
In the case of A transfer, before the IO bus cycle end signal indicates the end of the bus cycle, the memory bus cycle start signal is set to indicate the start of the bus cycle, and a memory address is output to the address bus; At the same time, when the IO bus cycle end signal indicates the end of the bus cycle, the data that has been temporarily stored in the DMA transfer i+t is output to the data bus, and then the memory bus cycle end signal indicates the end of the bus cycle. Before indicating the end, the IO bus cycle start signal is set to indicate the start of a bus cycle and an IO address is output to the address bus, and at the same time, when the memory bus cycle end signal indicates the end of the bus cycle, the data bus The above data is
It is characterized in that it is temporarily stored in the MA transfer device.

〔Example〕

Next, the present invention will be explained using the drawings.

Fig. 1 is a block diagram explaining the system configuration of a DMA transfer device according to an embodiment of the present invention, Fig. 2 is a timing chart in Fig. 1, and Fig. 3 is a state transition diagram of the button of this embodiment. It is.

In this embodiment, the two bus cycles DM explained in the conventional example are
By overlapping the read bus cycle and write bus cycle of A transfer, the time required for DMA transfer is shortened. That is, after starting a read bus cycle and before the end of the bus cycle, a write bus cycle is started with the preceding fj++n, then the read bus cycle is ended, and then a second read is performed before the end of the write bus cycle. By starting the bus cycle with advance control, the time required for the bus cycle is shortened.

In this embodiment, the bus cycle start signal (BCYST) is used as the bus cycle start signal MBY for the main storage section (memory) 4.
8Tt 3, Bus cycle start signal I for IO device ftZ
[lCYSTl Divided into 5 parts.

L Similarly, bus cycle extension signal (EADY) 1 = bus cycle extension signal for memory 4 I R kJA DY
It is divided into 16 parts.

AL output from DMACI) D9, M/IO, ■/
Each signal of address bus 11 including W is connected to IO device 2 through register 3 and to memory 4 through register 5. Data bus! 2 is the same as the conventional example (D
MACI. It is commonly connected to the memory 4 and the IO device 2.

DMACI is the first read/write in a two-bus cycle transfer.
Start a bus cycle. Read transfer (memory 4 to I
(transfer to O device 2), the bus cycle start signal l3 is first activated, and λDDR, R/W, M/IO
Each signal of the address bus 1l is output. The address to be read from memory 4 is output to ADDR, and R/W=
l, M/IO=1 is output.

Second, the bus cycle start signal l3 is made inactive and the IO bus cycle start (IBCYST) signal l5 is activated.
Activates and starts a write bus cycle, AD
Each signal II of DR, M/IO, and R/W is output.

ADDf'4 has IO boat 1 dress seven swords, R/W
=0%M/1 (outputs J=0.1 At the same time, MRE
AL) When the Y signal l4 becomes active, the data read from the memory 4 and output to the data bus l2 is
) Write to MACI's internal register.

Third, IBCYST signal 15 is made inactive, MBCYST signal 13 is made active, and 2
Starts the second read bus cycle, ADDi-t,
i also outputs signals 11 of /vV and M/IO.

The address to be read out for the second time from the memory 4 is output to ADDR, and W/W=l and M/IU=1 are output. At the same time, when the IREADY signal l6 becomes active, the data written to the internal register of DMACI in the read cycle is output from the internal register of MACl to the read data bus l2 and written to the IO device 2.

The fourth, fifth and subsequent addresses are the same as the second and third, but the memory addresses are sequentially added and subtracted. Write transfer (IO
(transfer from device to memory), the IBCYST signal 15tl is first activated and ADDi{,, R/W, M/
Each IO signal 1l is output.

Output the port address of the IO device to ADDR, and
/W=l, M/IO=0 is output.

Second, make IBCYST signal l5 inactive,
The MBCY8T signal 13 is activated to start a write bus cycle, and each signal 11 of AI) DJM/10, 1{/%' is output. Al) 1) Generally outputs the address to be written into the memory, and outputs ratio/W=0 and M/IO=1.

At the same time, when the Ii{,WAL)Y signal l6 becomes active, it is read from the IO device 2, and the data bus l2
The data output to DMACI is stored in the internal register of DMACI.

Third, make the MBCYST signal 13 inactive,
Activate the IBCYST signal l5 and start the second read bus cycle, AL)DR,l-L/W
, M/IO signals 11 are output.

Output the IO boat address to ADDR, R/W=l
, M/IO=Q. When it comes to MIL
When the EADY signal l4 becomes active, the data written into the internal register of the DMACI by the read cycle is read from the internal register of the DMACI, outputted to the data address l2, and written into the memory 4.

The fourth, fifth and subsequent addresses are the same as the second and third, but the memory addresses are sequentially added and subtracted.

When the IBCYST signal l5 becomes active, the IO device 2 receives ADDR, M/IO, 1{ /
Take in the W signal 11 and temporarily store it in register 3, then IHCY
This value is stored even after STl5 becomes inactive. The value of ADDR stored in the IO device 2 id register 3 matches the boat address of the IO device 2, and M/IO = 0.
Starts operation when . IO device 2 when R/W=1
Data is read from the data bus 12 and output to the data bus 12 of the system bus. When data is established on data bus 12 I
Activate R, EADYt 6.

Data is fetched from path 12 of the Tokisystem bus with R/W=0 and written into the IO device f2. When the writing is completed, the engineer EADY16 is activated.

When the MHCYST signal 13 becomes active, the main memory 4 takes in the M/IO and R/W signals 11 from the system bus and temporarily stores them in the register 5, and stores this value even after MBCYST becomes inactive. Main memory device 4P
The operation starts when /IO=1. When 1{,/W=1, the host t reads data from the address specified by ADDR in the device 4 and outputs it to the data bus l2 of the system bus. MREAD when data is confirmed on bus l2
Activate Yx4.

When tt7'w=0, data is fetched from the data bus l2 of the system path and written to the address specified by Al)DR in the memory 4. When writing is completed MREAi)Y
Activate l4.

A diagram showing the tying at this time is Figure 2. When the button in this figure is pressed and a DMA transfer is started, a read bus cycle tH is usually started. In this read passnicle tR, data D is read from the IO device 1 or memory and written to the internal register of DMACl.

Next, a write bus cycle tw is started.

In this write bus cycle tw, the data written in the internal register of DMACl in the read bus cycle is output to the data bus l2 and transmitted to the memory case or IO device.

The state transition diagram of FIG. 3 is a diagram showing the state transition of this DMAC. Click this state transition diagram to perform read transfer (transfer from memory to IO device) RBCY8T=MBCYS
T 1tRE A DY =~i}LEAi)YWBCY
8T=IBCYSTW EADY=IEADY Read address=memory address Write address=IO boat address is defined.

Time for write transfer (transfer from 10 devices to memory) BCYS'r = IBCYST ordinary EADY = IRE person DY WBCYST =. -MBCY8T WADY=MREADY Read address=I (J boat address Write address=Memory address is defined.

Initially, it is initialized to an idle state T i.

When a DMA transfer begins, it transitions to the TI state.

In this T1 state, ILHC YST is activated, the read address is output to ADL), and 1{, /W, and M/IO are also output in the same way. In the T21 state, RBCY8T is made inactive and WBCYST is
is activated and output to all write addresses. Similarly, R/W and M/IO are also output. RREAi
) Wait for Y to become active and DMA the read data.
Stored in internal register of Cl. l{, lL E A
When D Y becomes active, T if the transfer continues.
Transition to 12. To end the transfer, the process transitions to T i 2.

'1' In the 12 state, WBCYST is made inactive, RBCY8T is made active, and the read address is output to ADD l{,.Similarly, u7w,
It also outputs M/IO. Write data is successively output from the internal register of DMACl to data bus l2, and
It waits for DY to become active, and when this WREADY becomes active, it transitions to T21.

The Ti2 state is a state in which DM transfer ends, and l{, BCYST, and WBCYST are all inactive, and each signal 11 of ADDR, R/W, and M/IO is
− Set to high impedance. DMA write data
It outputs the data from the internal register of CI to the read data bus l2 and waits for Wl{, EADY to become active. W
When READY becomes active, it transitions to Ti.

As explained above, according to the present invention, even if it takes two bus cycle transfers, 1) MA transfer can be performed at high speed by overlapping the read bus cycle and the write bus cycle.

FIG. 4 is a block diagram showing the system configuration of a second embodiment of the present invention. In the first embodiment, the DMA transfer between the IO device and the main memory was explained.
As in the second embodiment, it is also possible to apply the DM person transfer from the main storage device to the main storage device.

In this embodiment, a dual port memory is used as the main memory device 7. The address bus and data path of DMAC6 are address bus 11 and data bus l on the system bus.
Connected to 2. The address bus and data bus of the first port l9 are connected to the address bus 111 on the system bus and the data bus l2, and the address bus and data bus of the second port l9 are also connected to the address bus l l on the system bus. f - connected to bus l2.

Connect the IO bus cycle start signal (IBCYST15) from DMAC6 to the bus cycle start signal of boat 19, and connect the bus cycle end signal of boat 19 to DMAC6.
IO bus cycle end signal (IEADYx6)
Connect to. Similarly, the memory bus cycle start signal (MBCYST13) from the L) MAC 6 is connected to the bus cycle start signal of the second port 20, and the bus cycle end signal of the baud 20 is connected to the memory bus cycle end signal (MBCYST13) of the DMAC 6. Connect to MREADY14).

According to the present invention having such a configuration, the read bus cycle and the write bus cycle are overlapped with each other in two bus cycle transfers, and D M from memory to memory can be performed at high speed.
Performing A transfer becomes "J function".

〔Effect of the invention〕

As explained above, according to the present invention, even if a two-bus cycle transfer button is pressed, the read bus cycle and the write bus cycle are overlapped, so that the data can be transferred at high speed.
This has the effect of making it easier to perform MA transfer.

[Brief explanation of drawings]

Fig. 1 is a system block diagram of a DMA transfer device according to an embodiment of the present invention, Section 2 is a timing chart of the DMA transfer shown in Fig. 1, and Fig. 3 is a state transition diagram of the DMA transfer device shown in Fig. 1. , @4 shows the block failure of the second embodiment of the present invention, and the fifth
The figure is a /stem block diagram of a conventional LAMA transfer device.
FIG. 6 is a timing chart of L) MA transfer in FIG. 5. 1, la, 6-・-DMAc, 2.
2 a--IO unit 1, 3.5...Register, 4
, 4a, 7...main memory section, 11...゜゜゜address bus, l2...data bus, 13...
...Memory bus cycle start signal, l4...
・Memory bus cycle ends 1ro, 15・゜゛...
IO bus cycle start signal, l6... IO bus cycle end signal, 17...DRQ% l8.
...D CK, 19...1st boat, 2
0...Second boat.

Claims (1)

[Claims] A DM that performs one unit of DMA transfer in two bus cycles: a bus cycle for reading and a bus cycle for writing.
A transfer device and IO supplied from this DMA transfer device
an IO device that connects a bus cycle start signal and an IO bus cycle end signal supplied to the DMA transfer device;
A main memory device that connects the memory bus cycle end signal supplied to this IO device and the memory bus cycle start signal supplied from the DMA transfer device, and an address bus and a data bus that are commonly connected to each of these devices. In the case of DMA transfer from the IO device to the main storage device, first, before the memory bus cycle end signal indicates the end of the bus cycle, the IO bus cycle start signal is set to indicate the start of the bus cycle. and input I to the address bus.
At the same time, when the memory bus cycle end signal indicates the end of the bus cycle, the data temporarily stored in the DMA transfer device is output to the data bus, and then the IO bus cycle Before the end signal indicates the end of the bus cycle, the memory bus cycle start signal is set to indicate the start of the bus cycle, a memory address is output to the address bus, and at the same time, the IO bus cycle end signal indicates the end of the bus cycle. When the data bus is in use, the data on the data bus is temporarily stored in the DMA transfer device, and in the case of DMA transfer from the main storage device to the IO device, first the IO bus cycle end signal indicates the end of the bus cycle. Before outputting a memory address to the address bus, the memory bus cycle start signal indicates the start of a bus cycle, and at the same time, when the IO bus cycle end signal indicates the end of the bus cycle, The stored data is once output to the data bus, and then, before the memory bus cycle end signal indicates the end of the bus cycle, the IO bus cycle start signal is set to indicate the start of the bus cycle, and the address bus 1. A DMA transfer control method comprising: outputting an IO address to a bus cycle; and at the same time, when a memory bus cycle end signal indicates the end of a bus cycle, data on the data bus is temporarily stored in the DMA transfer device.