JPS5963846A - Pulse transmission line coding method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse transmission method, and particularly to a transmission path coding method suitable for asynchronous time division multiplex transmission in which asynchronous pulse trains are synchronized and transmitted.

[Prior art]

Figure 1a shows a conventional method for synchronizing asynchronous pulse trains.
-The method shown in b has been proposed. ◎In other words, “1” in original signal pulse train a is “11” or 00.
"0" is encoded as "1" or "0", and when there is no signal, it is expressed as "111" or "000".

As can be seen from the figure, this transmission code does not satisfy the conditions for DC balance, and therefore it is necessary to perform further transmission line encoding to achieve DC balance before transmitting.

[Purpose of the invention]

An object of the present invention is to provide an encoding system that satisfies the conditions of DC balance as well as synchronization.

[Summary of the invention]

In order to achieve the above object, the present invention uses both a DC-balanced code within a block and a DC-balanced code by mode switching. The principle is shown in Figure 1C-(I).When converting a signal asynchronous to the bit period τ of a transmission signal such as a to a sign of 1 or an integer of pulses with period τ,
"1" of signal a becomes 11" or "00", 0" becomes 10" or 01", and when the signal to be changed is a blank (referred to as "E") that does not occur due to the relationship of the period. allows the pulses corresponding to E to be balanced within a certain block. Figure 1 C is one example, where °E" is "111000"
Or "000111".

Of these, only “1” in C is DC in the block.
Since r is not maintained, DC balance must be achieved by mode switching.

For d, "1" is "11" or "00", "0" is "01" or "10", and E is "0001" or "11".
10" or °1000" or "0111".

In order to construct an M pulse train, the following rules must be satisfied.

(1) If DC balance cannot be achieved within the block, DC balance is achieved by mode switching.

(2) The first and last codes in the block are different except for one of the "l"θ"Eo buildings.

(3) Select a mode so that a change point always occurs at a boundary point between blocks.

9 Examples of the Invention] The present invention will be described below using examples. FIG. 2 is a block diagram of an embodiment implementing the pulse transmission line encoding method according to the present invention. FIG. 3 shows the waveforms of each part of the transmitter of the above embodiment.

In FIG. 2, the original signal S is applied to the elastic memory 2. This is read out as "1"0" and "1.]" (empty signal) by the clock CRT (sending side read clock).

The clock C8 corresponding to the original signal S is supplied to the correction circuit l (sending 1
1111 clock position correction circuit), the position is corrected by the line clock Ct, and the write clock C
As WT (sending side write clock), the time point at which the original signal Sk is written into the elastic memory is determined.

The reason for performing this correction is 1.1) to avoid simultaneous loading and shifting.

λ Figure 2 Elastic memory, 1 read from Y.
The ``0'' and E'' signals are encoded in the encoding circuit 3. In this encoding circuit, a read clock pulse CRT is also generated at the same time.

The details of the clock correction circuit 1, the encoding circuit 3, and the elastic memory will be explained below using Figures 4 to 6, respectively.

FIG. 4 shows one embodiment of the clock correction circuit 1. The clock pulse Ct applied to the input terminal 10 is applied to one side of the AND circuit 15 via a constant delay circuit 11 to avoid overlapping with the output pulse. On the other hand, the No. 16 clock pulse C8 applied to the input terminal 12 is applied to the pulse expander 13, and its output drives the flip-flop 14 and inhibits the gate 15.

Pulse N' output q is performed by flip-flop 1
This is to prevent the setting and resetting of 4 from occurring extremely close to 141. The output of the flip-flop 14 is applied to a differentiating circuit (a combination of an inverter 16 and an AND gate 17) to obtain a write clock pulse CWT.

Next, the operation of the elastic memory 2 will be explained using Figure 5. In the figure, the signal pulse S is the memory 31 to 3
When the contents of the memory 31 are read out, the contents of the memory 32 are transferred and the contents of the memory 33 are transferred to the memory 32. A signal is stored in memory 32 only if the signal is already stored in memory 31.

The same applies to the memory 33.

Memories 41-43 are used to indicate whether or not a signal is stored in memories 31-33.

The above operation will be explained using FIG. 3. In the figure, when the waveform M1' is "on", it indicates that a signal is stored in the memory 31. M+ indicates whether the stored signal is "1" or not.

It shows whether

When M2' arrives at b, the memory 33 is already occupied, so the signal is written into the memory 34. Waveform M2 indicates whether the signal is "1" or "0".

The operation of preferentially writing data from memory 31 is performed using gates 34-39 and 45-47 as shown below.

First, the gate 45 allows the dF write pulse CWT'!il- to pass when the memory 41 is "OFF", so the memory 41 becomes "0" and the gates 34 and 35 are fully open, and the signal is If it is "1", the memory 31 is set, and if it is "0", it is reset.

The fact that the memory 41 is "On" means that the memory 31 is already occupied, so the gate 4
5 is open. Instead, the memory 42 is
''', the gate 46 passes the write pulse CWT and opens the gate 36.37, so the signal is written into the memory 32.The same goes for the memory 33. When the contents are transferred to the memory 42, 0'' is read from the input terminal 48 and the state becomes "OFF", which can indicate that the memory 33 is empty.

The signals read in as described above are read out as 1""0"Eo through all the gates 51 to 53 by the read clock CRT.As can be seen from FIG. Shift pulses for 33.41 to 43 are also used.

Next, the encoding circuit will be explained using FIG. Signals "1"0" and "E" read from the elastic memory 3 are applied to input terminals 61, 62 and 63 of the encoding circuit, respectively. A signal of "1" is delayed by twice the clock cycle (2T) by the delay circuit 65. 0'' results in two pulses delayed by T and 2T.

°E” is three pulses delayed by 3T and 6T.The result of combining these pulses at the OR gate 70 is the waveform S shown in Fig. 3.
t, and when the trigger type flip-flop 71 is driven with this waveform, an encoded waveform St is obtained.

The outputs of the slow circuits 65, 67 and 69 are combined by the OR gate 72 to form the readout cyclic pulse CRT shown in FIG. I can stay full.

I explained the transmitting section of Leahy 2nd L, '3. In this transmission, an asynchronous signal S is sent to the clock rail of the transmission line as well as a DC balanced signal Hj, S, 17. This signal reaches the receiver 14 via the transmission line 5.

Next, I will explain the 13th part of Uke's giII work. The signal received via the transmission path 5 is generated as a signal [1] by the regenerative repeater 101. From this regenerator, the regenerated clocks 102 and clocks 103 are transmitted to the decoding circuit 104.
supplied to The following operation will be illustrated using FIG.

FIG. 7(e) shows the reproduced pulse train (same as FIG. 3 S L), which is decoded by the decoder 104 as shown in FIG. 7(i) as described later. However, the waveform i) also includes the empty -+= signal in the form of a signal (the section indicated by the arrow). Therefore, it is necessary to remove this section. For this purpose, the empty signal (E) and detection signal (i) are used. This is the diagonal line 111 (1 from minute) of the endogenous pulse train (e).
The moxibustion is performed ft, thereby removing the shaded part kr' of the waveform (1\)(e). At waveform 0(), the pulse is “On”
The “” part indicates that No. 18°1” exists, and the waveform (
In t), the part where the pulse is "on" indicates that the signal "0" exists.The waveform (k) and the section where the force is "off" indicate that the signal is empty.

Next, convert this (k) and ()) into elastic memory 1
05, but the sky signal E cannot be read. On the other hand, the frequency pull-in circuit 106 generates a clock pulse CRR that breaks the same repeat wave number as the clock C8 of the 1'C original month. This can be done by counting the sum CWR' of the number of pulses (10 and (6)) and controlling the frequency of the oscillator so that the count becomes equal to the count number of 8 light output clock pulses CRR. In the pulse correction circuit 107 has the same function as the pulse correction circuit 1 to prevent the write pulse CWR and the read pulse C+tR from occurring at the same time.The auxiliary clock pulse CRR'ld supplied for this purpose has a repetition period that is an integral multiple of the read clock pulse CRR. It's well set up.

It is clear that the conventional technology can be used as is for the regenerative repeater 101 and the frequency pull-in circuit 106; the elastic memory 105 is the same as the elastic memory 2, and the pulse correction circuit 107 is the same as the pulse correction circuit 1. Therefore, here, the decoding circuit 104
We will only describe the information and its operation in detail.

An embodiment of the decoder is shown in FIG. The reproduced signal applied to the input terminal 120 (FIG. 7(e)) is determined at the gate 122 exclusively as it has passed through the delay line 121 having a pulse repetition synchronization bottle delay time ('I'/2). A logical sum is taken to generate the waveform shown in FIG. 7f. This waveform and its inverse are applied to shift registers 123 and 124, respectively, which use word-synchronized clock pulses (FIG. 7(g):
(The method of generating -' will be described later), so the waveform of the first stage of the shift register 123 is as shown in FIG. 7Q. Since this waveform includes an empty signal as described above, it is necessary to remove this. For this purpose, the empty signal detection circuit 125 is used. This circuit has a delay time 'l'/
2 delay circuits 126 are used, and the outputs and outputs whose polarities are inverted by an inverter 127 are logically operated by an AND gate 128 and an OR gate 129, and the 7th delay circuit 126 is used.
The shaded area in Figure (a) is detected and the detection pulse (Figure 7 (j
)) is what you get. The reason for the extra delay circuit is to adjust the time of the detection pulse.

By resetting the shift registers 123 to 124 with this detection pulse, the empty signal portion can be removed as shown by diagonal lines in FIGS. 7(a) and (4). This waveform is the output of D-type flip-flop 132. The output of the output terminal 134 of FIG. 8 is added to the output of the elastic memory 105 of the decoder 104 of FIG. 2. Although not shown in the figure, in order to read this into the elastic memory, the outputs of output terminals 133 and 134, that is, waveforms 00 and (4) (Figure 7).
The logical product of the complete combination and the clock pulse Ct is used for CWR'. This is read out by the output CRR of the frequency pull-in circuit (Fig. 7, 1i), and shown in Fig. 7(n).
Change the shape of the knot to 0L.

Word synchronization of the clock pulse 135 (FIG. 7g) for driving the shift registers 123-124 and the D-type flip-flop 132 will now be described. This clock pulse is obtained by dividing the frequency of the original clock pulse 130'i) by a trigger type flip-flop 132, but the phase of the outer periphery is determined by the fall of the empty signal detection pulse (FIG. 7f). It can be shortened by resetting 131. In Figure 7, the frequency-divided clock (Figure 7 g) is "off" at the falling edge of the empty signal detection pulse (Figure 7 j), so it has a normal phase, and the phase adjustment It can be seen that word synchronization is achieved without being performed.

〔Effect of the invention〕

As described above, according to the present invention, in the process of synchronizing the asynchronous signal ', a code can be generated to balance the DC current, so that it can be sent as is to the transmission line. That is, since synchronization and line coding can be achieved simultaneously, this is highly effective in practical use for flexible and efficient synchronized transmission or synchronized multiplex transmission of asynchronous signals.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of the configuration of an embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the principle on the transmitting side, and 6 to 6 are all configuration diagrams of the transmitting side number block of the embodiment of the present invention, FIG. 7 is a waveform diagram for explaining the principle of the receiving side of the actual sister example according to the present invention, and FIG. 8 is a diagram showing the implementation of the present invention. FIG. 3 is a configuration diagram of a receiving side decoding circuit in an example. 1.107...Pulse correction circuit, 21 105...
Elastic memory, 3... Encoding circuit, 101.
...Regenerative repeater, 104...Decoding circuit, 106...
Frequency pull circuit. ■2 f iI o1) Kue ikan 1 t53 (2) ,5 ■■-■--1---Cs "-1l 1 1-■Yo1-E'□ t sp X\ Ward No. 4 Figure 6 ■ Figure 5

Claims (1)

[Claims] In a pulse transmission line encoding method that synchronizes and transmits asynchronous signals by encoding 1, l'', 0°, and an empty signal ``E'', 0'' and ``0'' are transmitted. In each block encoded with E'', except for one type, the states of the first and last pulses in the block are different, and if the DC balance cannot be achieved within the block, the DC balance is achieved by mode switching, and the A pulse transmission line coding method characterized in that a mode is selected so that a change point always occurs at a boundary point between blocks.