JPS596645A - Method for transmitting of voice packet - Google Patents

Abstract

PURPOSE:To obtain a packet communication system with high quality even if the delay of a voice packet is varied, by adding sound starting information to the voice packet to process the voice packet. CONSTITUTION:A start information generator SPG adds starting information to a packet. Receiving a control signal S119 in each voice data block, the SPG supervises a control signal S118 outputted from a voice detecting circuit VDET to detect a voice data block corresponding to voice starting out of respective voice data blocks. The starting informatiin dlt is supplied to a voice packet transmitting circuit PVT through a data line 115 and used for the assembling of the starting information field of the voice packet. In a voice data block discriminated as voice, a transmission control signal tpt is supplied to a packet transmitting circuit PUT and the corresponding voice data vdt, sequential- number sqt and starting information dlt are supplied to the PVT and assembled as a voice packet to be sent to a data line 111.

Description

[Detailed Description of the Invention] The present invention relates to a voice and voice transmission system that converts and transmits voice signals in order to perform highly efficient communication, and particularly relates to voice quality when decoding voice and voice signals. It is related to the improvement of

In recent years, a system has been realized in which audio is converted into audio signals using the PCM system, etc., and then converted into audio signals and transmitted and received via a digital exchange device. When transmitting audio by converting it into packets, in order to increase the transmission efficiency or reduce the processing amount of the voice exchange device, only the active voice is converted to ξ
A common method is to keratize the signal and transmit it. This method also takes advantage of the fact that there are no packets to be transmitted during silent intervals, and inserts facsimile data or combiner data from a data terminal into this interval, thereby transmitting voice and data simultaneously. It also has the appeal of being able to build communication systems. In a method in which only voiced parts are packetized and transmitted, and silent parts are not transmitted, it is necessary for the sending side to notify the receiving side of the presence, length, etc. of the silent parts. This is because silence is an important part of the voice, and the voice cannot be decoded without faithfully reproducing the silent section. For this reason, conventionally, on the calling side, firstly, the voice is formed into a voice processor at predetermined intervals, regardless of whether it is voiced or silent, and a serial number is sequentially assigned to each voice block 0 and 7.
Next, it determines whether each audio data block is voiced or silent, and only those with voice are sent out as audio/guicerato. Then, a memory is provided on the receiving side, and the 9 voices are temporarily stored in the memory, and the voice voices with the serial numbers are sequentially read from the memory, decoded and played back, and the voices corresponding to the missing numbers are reproduced. In response to this, we should use a method to generate silence on our own and receive it.Even if Gukerato arrives a little later, it can be temporarily stored in memory so that the playback side can play back the signal without inserting silence itself. Then, z′? It was equipped with a function to prevent decoding and reproduction quality from deteriorating due to fluctuations in packet reception timing. A typical method for preventing voice quality deterioration due to reception timing fluctuations is to receive a nosocket (hereinafter referred to as a voice start), which is the beginning of the voiced part of the voice, and store the packet in memory from that point onwards. The packets are retained for T time, and the packets that are sequentially received thereafter are also stored in the memory, and after T time has elapsed, they are read from the memory and decoded at the same time interval at the same rate as when the packet was generated. Conventionally, in this type of system, there is no easy way to detect the start of a voice, the beginning of a voice, and the l- is not detected, so there are no packets stored in the memory, and silence is automatically inserted and decoded and played back. There was a problem in that all packets received while the system was running had to be treated as non-voice beginnings/guikeratos, even if they were non-voice beginnings/guikeratos. In other words, in the conventional method, when the voice packets of the active part transmitted continuously from the transmitting side are intermittently delayed due to delay fluctuations in the packet switching network, the voice packets that arrived late are It is mistakenly treated as a voice start packet and is delayed in memory on the receiving side for a certain period of time, resulting in unnecessary silence being generated and the greatly delayed voice packet being decoded. Although it would be natural to discard packets that arrive too late, they have the disadvantage that they are forcibly delayed for a certain period of time and then decoded. Furthermore, in this method, if we try to discard the voice message, we must detect that the delay in the arrival of the voice voice message is too great in time for decoding in the above situation. If the circuit becomes complicated and you try to discard a packet by implementing the timing detection described above, if all packets after that packet are delayed enough to require discarding, the effect of discarding the packet will be reduced. It is difficult to keep the circuit within the range of the sound part, and when these considerations are taken into account, the circuit Ftl becomes quite complex and cannot be implemented easily.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and its purpose is to provide an audio packet transmission method that makes the audio/guicerto decoding device simple, compact, and inexpensive, and provides excellent audio quality. It is.

The feature of the present invention is that the transmitting side can
, in audio packet communication in which only Q packets are sent, the audio packets are temporarily stored in a memory provided on the receiving side, and then decoded into audio, when 79 audio packets are not stored in the memory, the sound part of the audio is If a voice packet with parts other than the beginning part turned into ``Gkerat'' is received, then the voice packet is discarded, and if other than the above, the received voice is・After temporarily storing all the ``Gukerat'' in the memory, it is decoded into an audio signal.

Examples will be described below with reference to the drawings.

Figure 1 shows the voice and voice transmission system of the present invention.
9 is a block diagram illustrating an embodiment of the communication system, in which numeral 20 is a voice/kerat transmitter, 202 is a voice/kerat receiver, and 30 is a voice/kerat transmitter 201 and a voice/wire receiver. A packet terminal consisting of a kerat receiver 202, 2203 a telephone, 112 an analog signal line, and a CO
D is an encoder, B is a buffer circuit, VDET is a voice detection circuit, BLK is a blocking circuit, SNC is a serial number counter,
SPG is a start information generator, PVT is a voice packet transmission circuit, 121, "2ANDK-1, 111, 113,
114.115° 117 is a data line, 1 '16 is a control signal line, vat is the original voice signal from the telephone 203, vd
t is audio data, sqt is serial number, alt is start information, t
pt is a transmission control signal, pt is a transmission packet F, 811B is a control signal output when the voice detector VDET detects voice and the voice is a sound block, 5119 is a blocking circuit BLK blocks one block of data. 5120 is a control signal outputted by the blocking circuit BLK with a slight delay from the control signal 8119; 20
4 is a transmission line, 205 is an audio/o-quesokera communication section, 2
06 is a voice packet receiving section, 302 is a packet terminal consisting of a voice/kerato transmitter 205 and a voice/kerato receiver 206, PVR is a voice/9 kerato receiver circuit, R
is the read address counter, W is the write address register, SP is the start detector, DET is the detection circuit, Ding is the write index supply circuit, M is the memory, 8M is the silent memory, TIM
is a timer circuit, CK is a clock circuit, DS is a switch, D
EC is a decoder, WCL is a write control circuit, and RCL is a read control circuit.

13.14. ．． 15.19, 21, 22.23 are data lines, 2θ is an output line, 12 is an analog signal line, 16 is a write control line, 207 is a telephone, pr is reception Δcare 1, v
dr is active voice data, sqr is a serial number, dlr is start information, wp is a write control signal, var is an original voice signal that is marked and sent to the telephone 207, S17 is a read address signal that is the output of the read address counter R, 818 is a write address signal that is the output of the write address reno star W, S24 is a sound start signal that is output when the start information detection i sp detects that the start information dir is a sound start, and S25 is a sound start signal read by the detection circuit DET. Address match signal output when address signal S17 and write address signal 81B match, S26 is write control circuit WCL
is a write control signal output in response to the states of the sound start signal S24 and address match signal S25, and S27 is a write control signal outputted by the write control circuit WCL in response to the state of the sound start signal S24 and address match signal S25.
828 is a time limit signal that the timer circuit TIM outputs after T time has elapsed since receiving the input of the control signal S27; S29 is a clock signal;
S30 is a read control signal that the read control circuit RCL outputs in response to the states of the output line 20, the address match signal S25, and the time signal S28, and 8.91 is a read control signal output by the switch DS when the data m
S32 is a selection signal for connecting one of data line 21 and data line 22 to data line 23;
This is a control signal that controls the data output to. The voice packet receiving section 202 of the packet terminal 301 has the same configuration as the voice packet receiving section 206 of the packet terminal 302, and the voice packet transmitting section 205 of the packet terminal 302 has the same configuration as the voice packet transmitting section 20 of the iRcare) terminal 301. They have the same configuration.

The voice packet communication system shown in FIG. 1 is divided into a packet terminal 30 and a packet terminal 302, and each packet terminal is connected to a packet switching network (not shown) via a transmission line 204 to perform voice communication. However, the configuration and operation of each packet terminal are the same, and the overall operation will be made clear by explaining voice communication on one side. Only the operation of transmitting a voice packet from the terminal 302 and receiving the voice packet at the packet receiving unit 206 of the Noyaket terminal 302 will be described.

First, the operations of the audio/video transmitter 1 to the transmitter 201 will be explained. The original voice signal vat from the telephone 203 is sent to the encoder C.
The signal is applied to OD via an analog data line 12 and converted into, for example, a PCM audio input signal. The blocking circuit BLK recognizes that a plurality of samples of the converted signal, that is, the audio data has been encoded. This is because the output data line 117 of the encoder COD is supplied to the blocking circuit BLK. As a result of the recognition, the blocking circuit BLK sends the control signal S 119 to the voice detection circuit ET.

While supplying the buffer circuit B1 to the serial number counter SNC and the start information generator SPG, the control signal 5120, which is output slightly later than the control signal 8119, is sent to the gate circuit 12.
Supply to 1. The control signal 8119 and the control signal 5120 are outputted each time the encoder COD encodes a plurality of data blocks, that is, each time the data is divided into audio data blocks. The data line 117 is
It is also supplied to the projection circuit VDET, and the audio detection circuit VDET
monitors the audio level of the audio data block and detects whether the data processor is loud or silent. This operation is performed by the control signal 5 output from the blocking circuit BLK.
119 and is performed for each data block.

The voice detection result is notified to the start information generator SPG and the anchor point 121 by a control signal 5118. 87
77 circuit B temporarily parses the audio data while the audio detection circuit VDET detects whether the audio data block is voiced or silent. The buffer circuit B supplies the buffered audio data to the audio packet transmitting circuit PVT as audio data vdt via the data line 113 in response to the control signal 8119 outputted from the processing circuit BLK. The audio data vdt is used for assembling a 29-voice T4 voice cheetah field inside the voice transmission circuit PVT, as will be explained later. On the other hand, the serial number counter SNC counts the serial number for each data processor. The serial number counter S
The increment of NC is performed by supplying control signal 5119 to serial number counter SNC. Serial number counter SN
The output of C is supplied to the audio/set transmitting circuit PVT via the data line 114 as a serial number sqt, and when each audio data block is assembled into audio data blocks, the serial numbers ■, ■
, ■, ■... are attached. That is, the serial number sqt is used for assembling the serial number field of the voice/mother packet inside the voice transmission circuit PVT, as will be explained later. The start information generator SPG is used to add start information to packets, which is a feature of the present invention, and receives the control signal 5119 for each audio data block and monitors the control signal 8118 output from the audio detection circuit VDET. Among each audio data block, the one corresponding to the start of a voice is detected. In other words, the start information alt is set to "1" for the first data block among a group of data processors in which sound data blocks are continuous, and the start information alt is set to "1" for the other data blocks.
10''.

The start information alt is supplied via the data line 115 to the voice and voice transmission circuit PVT. As will be explained later, the start information alt is used to assemble the start information field of voice and voice within the voice and voice transmission circuit PVT. Audio/Guke, 1/Transmission circuit PVT is audio data v
dt, serial number sqt, and start information charge t, and after assembling it into a voice packet according to a predetermined frame of 1., it is transmitted via the data line 111 as a voice 2f packet pt. Voice/Kerato transmission circuit pv'
Activation of the r.9 kerat assembly/transmission operation is performed by inputting the transmission control signal tpt via the control line 116. The transmission control signal tpt is sent to the blocking circuit BL.
It is supplied from K for each audio data block, and the blocking circuit BLK and the audio/kerato transmitting circuit PV
In the middle of T there is an AND CATE 1. i'l is inserted, and when the voice data block corresponds to a sound state, a control signal 811B is output from the voice detection circuit VDET, and the control signal 8
118 and the control signal S 120, the control signal 5120 can be used as the transmission control signal tpt for the audio/video signal.
When the voice data block corresponds to silence, the control signal 8118 of the voice detection circuit VDET is not output and the AND logic cannot be obtained, so the transmission control signal tpt is supplied to the voice and voice transmitter circuit PVT. is not supplied. That is, for the audio data block determined to be active, a transmission control signal tpt is supplied to the voice data transmission circuit PUT, and the transmission control signal tpt is sent to the audio data line 11 corresponding to the audio data processor block sqt.

The start information d]t is supplied to the packet transmission circuit PVT, assembled into a voice packet, and transmitted to the data line 11. On the other hand, for a data block determined to be silent, the transmission control signal tpt is blocked by the AND gate 121 and is not supplied to the audio/video transmission circuit PVT, so that the audio data vdt corresponding to that block is transmitted.

Serial number sqt and start information alt are data lines 113, 11
4° 115, and the audio packet corresponding to the audio block does not appear on the data line 111.

FIG. 2 is a frame configuration diagram of the voice IP packet on the data line 11. In FIG. 2, 41 is a control information field having control information hd created inside the voice packet transmission circuit PVT, 42 is a start information field having a start information charge t on the data line 115, and 43 is a data line 114
The serial number field 44 has the serial number sqt above, and the audio data field 44 has the audio data Vdt of the data line 113''-. Packet start information alt is a feature of the present invention, and since the output data line 115 of the start information generator SPG is supplied to the audio/guicerto transmission circuit PVT, when the start information alt = 1, the audio data block ( When the start information dlt=0, it indicates that the voice iP (key, cut) is a sound start nokke, g, and when the start information dlt=0, it is a sound start other than the sound start A, g. The explanation of the operation of the receiving section is that the setting of the voice start control field 42 in the voice signal makes a great contribution to the packet decoding process by notifying the receiving side of the voice start information. Explain in detail.

FIG. 3 is a diagram for explaining the transmission operation of the packet transmitter 20 in more detail, and (a) shows the original audio signal vatX(
b) is audio data vdt obtained by encoding and blocking the original audio signal vt, ■, ■, ■, ■... is the packet serial number 3qt, and (c) is whether the audio gutter shown in (b) is voiced or silent. The output of the voice detector VDET showing (d) is the starting information generator SPG which creates its leading edge from the signal shown in (c).
(e) is the transmission pulse tpt 1 (f) is the transmission pulse at the output 111 of the 9-kerato transmitter circuit PVT. The solid line portion in FIG. 3(f) indicates a voice packet, and the diagonally shaded portion of the voice packet indicates a voice start packet. The dotted line is silent voice/gukerato and is not transmitted from the transmitting side, but is shown for the sake of explanation. As explained above, the serial number sqt is assigned to each of the above groups, and in the case of Fig. 3(f), ■■
■■■[F]■ is transmitted as a voice packet. It is the serial number counter SNC that repeats the serial number ■■...■
This is because a mono-mouth 8 counter was used. Figure 3 (
The voice packets sent as in f) are sent to the receiving bucket via the packet network (not shown) and the transmission line 204.
The voice packet reception unit 206 arrives at the voice packet receiving unit PVR as a voice packet pr.Next, the operation of the voice packet reception unit 206 will be explained. The voice packet receiving device PVR transmits the serial number of the received voice packet to the data line 14.
output as sqr to data line 15, and output start information to data line 15 as dl
r, the audio data is outputted to the data line 13 as vdr, and a write control signal wp created corresponding to the audio packet is outputted to the control line 16. In other words, the voice packet receiving device PVR performs the operation exactly opposite to the voice packet transmitting device PVT, and the voice data vdj% serial number sqt and start information alt transmitted on the transmitting side are converted to the voice data vdr, serial number s on the receiving side.
qr is received as start information dir, and a write control signal Wp is generated and supplied to the write control circuit WCL. The serial number sqr is set in the write address renostar W by the control signal 826, and the write address signal S18 output from the write address renostar W becomes the write address to the memory M. Furthermore, since the control signal 82.6 is supplied to the memory M as a write control signal for the memory M, the active voice data vd is sent to the write address of the memo IJM specified by the write address signal S'18.
r is written. When the voice data vdr is written to the memo IJM, a write index indicating that valid voice data has been written to the write address is set to "1" and is written to the same address as the write address. This operation is performed by the write index supply circuit (2), which outputs a signal "1" to the data line 19 in response to the control signal S32 output from the memo 'JM in synchronization with the writing of the audio data vdr to the memo IJM. It is done by The write index is used, as will be explained later, to determine whether to read voice data with voice from the memo IJM or read silent data from the silent memo 'JSM. The above series of operations is started by the write control signal wp being supplied to the write control circuit WCL, and thereafter, every time the write control signal wp is generated, the audio data vdr is written with the serial number sqr as the write address to the memory M, and the corresponding Set the write index of the write address to “1”
and sequentially store it in the memo IJM. When there is no output from the detection circuit DET or from the start information detector sp, the audio data vdr is written into the memory M as described above.

Memo I) M has an area for storing audio data of a plurality of predetermined audio packets. - As an example, FIG. 4 shows a memory configuration in the case where the number of areas for storing blocks of audio data vdr is eight. In FIG. 4, 45 is a memory address specified by the write address register W or read seat address counter R, 46 is a write index area, and 4
7 is an area for storing audio data vdr. In order to write the audio data vdy, the data line 13 is connected to the audio data vdy.
Data line 2 is used to read dr, data line 19 is used to write the write index, and output line 20 is used to read the write index.

Next, reading the audio data vdr from the memo IJM will be explained. Read control circuit RCL is clock circuit C
When the clock signal S29 of K is received and a predetermined reading time comes, the reading is instructed by the reading control signal S30, and the memory M outputs the audio data vdr at the address specified by the reading address signal S17 to the data line 2. At this time, the write index of the address is output to the output line 20, so whether the write index of the address is "1" or "0" is read and checked by the read 9 control circuit RCL. When the write index is "1", the control signal S31 instructs the switch DS to connect the data line 21 to which the audio data of the address is output to the data line 23, and the memory M
The audio data vdr from is sent to a decoder DEC, where it is decoded into a voice signal. At the same time, the write index supply circuit (■) outputs a signal "0" to the data line 19 indicating that the data has been read, and the memo IJM receives this and sets the write index to 1.
Rewrite it to 0. When the writing index is 0, silent memo I
A control signal 831 is output to connect the read data line 22 from the JSM to the data line 23, and the silent data is sent to the decoder DEC and decoded into a silent signal. Memo IJM
At the time when reading audio data from the silent memo IJSM or reading silent data from the silent memo IJSM ends, the address counter R receives the control signal S30 and increments by +1. When there is no output from the detection circuit DET or timer circuit TIM, the write index is sequentially read and inspected as described above.
Depending on the result, if audio data is written in the memo IJM, the sound data is decoded by reading it from the memo IJM, and if no audio data is written, it is silent. decode the silence by reading the data from the silence memory. As explained above, the serial number aqr
The original audio signal var is written by using the write address as the audio data vdr and writing it into the memory M with a writing index, and then decoding the sound data or silent data according to the instruction of the write index according to the read address counter RvC.
is obtained and sent to the telephone 207 and reproduced as audio.

Next, the time interval of the voice packets arriving at the voice packet receiving device PVR varies, so that the voice packet receiving device PV
A case will be described in which the time intervals of the serial number sqr, start information dlr, and audio data vdr% write control signal wp output from R are not constant. There is a delay in the packet switching equipment that constitutes the 79-bit switching network (not shown) before a packet sent from the sending side reaches the receiving side, and the delay is 1? Generally, it is not constant depending on the Kent. However, in the transmission of voice and keratin, smooth decoding is not possible due to variations in delay, which not only causes deterioration of the voice but also, in extreme cases, may make communication impossible. For example, if you perform an operation to immediately transfer the audio data vdr written in the memo IJM to the decoder DEC, and the next audio data vdr arrives later, the audio cannot be decoded (insert silence). It is also clear that it causes inconvenience (unavoidable). Therefore, when decoding to the original audio, it is essential to absorb variations in delay time on the decoding side.・The absorption of fluctuations in the delay of the zokerato is generally done as follows. In other words, the permissible time for preventing conversation between callers from becoming unnatural, e.g. 1
A method may be adopted in which the audio data is kept in the memo IJM for a time-conscious manner, delayed, and then transferred to the decoder 5 DEC. In order to realize the intentional delay, the detection circuit DET and the timer circuit TIM function as follows.

The detection circuit DET detects a match between the write address register W and the read address counter R, and when the two match, a match signal 825 is obtained. The address match signal is supplied to the write control circuit WCL and the read control circuit RCL. Now suppose that one silence continues for a relatively long time (Note 17
(at least to the extent that all the audio data in M can be read) At the beginning, the audio data VDR or silent data is decoded, but after that, no packets are received, so the kerato receiving device P is used for audio data.
Since no signal is output from VR and therefore the write register W is fixed up to 1, the read address counter R will eventually catch up with the contents of the write address register W and become the same address. Here, the detection circuit DET detects a match between both addresses and notifies the write control circuit WCL and the read control circuit RCL. The read control circuit RCL interprets the coincidence signal as that there is no audio data in the memory M, and thereafter stops incrementing the read address counter R.
The control circuit RCL switches the switch DS to the silent memo 98M side, reads the silent information from the silent memory SM, and sends it to the decoder DE.
Instruct C to decode the silence information. In the above state, when the voice 9 bits with the start information dlr=1 newly arrives at the voice packet receiving device PVR and generates the write control signal, the detection circuit DET outputs the address match signal S25.
and the start information detector sp outputs the sound start signal 824.
Therefore, the write control circuit WCL outputs the control signal 827 to the timer circuit TIM and the read address counter R.
, the timer circuit TIM instructs the read control circuit RCL to decode the silence for a defined T time, and the read address counter R loads the serial number sqr. Then, after the elapse of time T, the audio data in the memory M is read using the sqr loaded into the read address counter R as the read address, and decoding is started. Therefore, the transfer of the audio data vdr to the decoder DEC can be delayed by T time. Therefore, there is no need to insert silence even if the arrival of packets or packets is delayed, and fluctuations in packet delay can be absorbed. On the other hand, in the above state (the state in which both the addresses of the read address counter R and the write address register W match), a new voice/gukerato with start information dir=o arrives at the voice/gukerato receiving device PVR. When generating the write control signal wp, the detection circuit DET sends out the address match signal S25, and the start detector SP does not output the start signal S24, so the write control circuit WCL uses the write address register W and the read seat address counter R. The audio data is discarded without being written into the memory M by omitting any operation for the audio data. In other words, when the memory M is empty with no audio data and the start information dlr=o audio/('kerat is received, the audio packet is discarded as one with a large delay.In the sense of summarizing the above explanation, the fifth FIG. 6 shows a flowchart of the operation of writing voice packets into the memory M in the voice packet receiving section 206, and FIG. When it arrives at the voice/guikerato receiving device PVR, the operation as shown in FIG. When the data read time comes, the operation shown in FIG. 6 is performed under two conditions: the address match signal 825 which is the output of the detection circuit DET, and the time limit signal 82B which is the output of the timer circuit TIM.

Write address register W and read 9 address counter R
In addition to the above-mentioned conditions, the matches occur when the write address register W catches up with the read address counter R. This occurs when the number of voice packets received exceeds the storage area of the memory M, and in this case it is advantageous to discard old data in order to maintain the naturalness of the conversation. Detection circuit DET
When detects address matching, next start information dlr=1
The address match signal S25 is held until the packet is received, and the read control circuit RCL does not update the read seat address counter R and instructs the silent memory SM to read the silent data. At this time, when the ekerat (with start information dlr=o) arrives, it is discarded, and when the eket with start information dir=1 arrives, the timer circuit TIM, read address counter R2, and write address register W are set as shown in FIG. , and the audio data VDR is sequentially memo U.
This means that the old audio data vdr written to memory M has been discarded.

As explained above, in the embodiment of the present invention, the transmitting side can record the sound part of the audio. In voice packet communication in which only the voice signal is sent and the voice signal is temporarily stored in a memory M provided on the receiving side and then decoded into voice, the voice signal is divided into blocks and a voice signal is generated in each block. A voice detector detects whether or not there is a voice signal, and when a voice signal of a voice is detected, the voice processor is activated.

The information is sent as voice and 9-bit. At that time, when packetizing the head part of the sound part of the sound with respect to the sound start control field provided in the audio notebook, the sound start control field is set to the first state (start information alt as the sound start voice packet). = 1), and when converting a part other than the beginning of the voiced part of the voice into a kerato, the voice start control field is set to the second state (start information alt=o as a non-voice start audio packet). ). If a non-speech start packet is received when there are no packets stored in the memory M provided on the receiving side, the voice packet is discarded, and in other cases, the received voice z'? By simply storing packets in the memory M for a certain period of time, it is possible to discard audio packets that have a longer delay than specified and which would otherwise have a negative impact on decoding, and it is also possible to It becomes possible to provide a voice packet communication system with excellent quality and absorption capacity. In addition, when there is no accumulation of ``Gukerat'' in the memory, there is no need to use a complicated timing circuit that takes into account the arrival time and serial number of ``Gukerat'' to determine whether to discard the voice packet that arrived late. Since it is only necessary to add the sound start information to the audio packet and make a determination, the hardware can be simplified.

Furthermore, after that packet after Aru Gukerat,
If all Gukerato are delayed to the extent that they need to be discarded,
Since the discarding of voice packets can be completed by receiving the next voice start packet, discarding of delayed voice packets can be minimized.

Also, if the voice start packet is lost within the network, it will cause problems in discarding the packet and decoding it, but as a countermeasure, if the transmitting side generates two or more consecutive voice start packets and transmits them. The probability that all of the voice start/start messages are missing is extremely small, and the occurrence of inconveniences is greatly reduced. Even when connected to a network where there is a high possibility of missing start/start messages, stable operation can be expected, and decoding becomes easier. This has the effect of preventing deterioration in quality.

The present invention makes it possible to realize a voice and voice communication system with excellent quality even when the voice and voice delay varies by simply adding voice start information to voice packets and performing simple processing and operation. It is possible to guarantee sufficiently stable operation even in the case of missing audio/guicerato, so the audio 11fl
It can also be applied to complex communication systems that process communications and data communications together.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a specific configuration of a voice packet, and FIG. 3 is a further explanation showing the transmission operation of the voice packet transmitter 201 in FIG. 1. 4 is an explanatory diagram showing the configuration of the memo IJM shown in FIG. 5 is a flowchart showing an operation of reading audio data from memory M in packet receiving section 206. 201.205...Voice packet transmitting unit, 202°206...Voice packet receiving unit, 301,302...
・Nokket terminal, 203, 207...Telephone, 12.112...Analog signal line, COD...Encoder, B...Pants termination circuit, VDET...Voice detection circuit, BLK... Blocking circuit, SNC... serial number counter, SPG... start information generator, PVT...
Audio A kerato transmission circuit, PVR...Voice packet receiving circuit, R...Reading sear address counter, W...Writing atto vy, v'y star, sp...Start detector, DE
T...detection circuit, ■...writing index supply circuit, M.
...Memory, SM...Silent memory, TIM...Timer circuit, CK...Clock circuit, DS...Switcher,
DEC...Decoder, WCL...Write control circuit, R
CL...Reading control circuit, 11, 13.14, 15°19.21, 22, 23, 111, 113, 114°1
15.117...Data line, 20...Output line, 16
．． 116... Control signal line, 204... Transmission line,
vat, var...original audio signal, vdt, v
dr...audio data, sqt + Sqr'' serial number,
dlt, dlr - start information, tpt...transmission control signal, pt...transmission Δ, g, pr...receiving, g, wp...writing control signal. Patent applicant Oki Electric Industry Co., Ltd. (C) + (+1 at Procedural amendment (Mutsu) ■ Indication of the case 1982 Patent application No. 115613 2 Name of the invention Audio packet transmission method 3 Person making the amendment Related Patent Application Personnel Office (105) 1-7-12 Toranomon, Minato-ku, Tokyo Address (105) 1-7-12 Toranomon, Minato-ku, Tokyo
Contents of amendment No. 6 within Oki Electric Industry Co., Ltd. (1) On page 14, line 8 of the specification, r PUT J is amended to r PVT J. (2) On page 18, line 18 of the same book, replace the word “output or” with 1
Correct it by saying "There is no output or there is no output." (3) On the same page, line 19 of the same book, the phrase ``There is no output'' is corrected to ``There is output.'' (4) In the same book, page 2:3, line 19, ``・yarus WPj'' is corrected to ``pulse wp j.''

Claims (2)

[Claims] (1) The transmitting side sends out only the voice/speech of the active part of the audio signal, and the receiving side temporarily stores the voice/speech in a storage section and then decodes it into an audio signal to account for fluctuations in transmission delay. In the audio packet transmission method that absorbs audio packets 1 and 1 received when the storage section provided in the receiving section is not empty, and voice packets 1 and 1 of the beginning of each sound part received when the storage section is empty, sound start voice packet)
are temporarily stored in the storage unit and decoded into audio signals, and when the storage unit is empty and receives audio packets other than the voice start audio packet, the received audio packets are discarded. Voice/Gukerat transmission method. (2) Kerat transmission to the voice as set forth in claim 1, characterized in that the fact that it is a voice start voice or kerat is notified by a voice start control field provided in the voice/main box. method.