JPS5969941A - Integrated circuit testing equipment - Google Patents

Abstract

PURPOSE:To test a plurality of IC's under the state in which they are fixed to the same frame at the same time, and to shorten a test time by transmitting a fixed input to test circuits, checking the synchronous states through succeeding checks while transmitting the same test input data and deciding acceptables or defectives by each comparing the results with a reference value. CONSTITUTION:An input pattern data regarding some test item is transmitted over each driver-comparator 161-165 from a timing selector 13, and each converted into analog signals in the comparators and transmitted simultaneously over each IC 11-14 and 10. In this case, each IC and 10 generate test output signals, and the output signals are converted into digital signals by several driver-comparator 161-165 and memorized to output pattern data memories 181-185. In a digital comparator 20, a storage data from the output pattern data memory 185 for the standard sample IC10 and each storage data from the output pattern data memories 181-184 for test ICs are each compared simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an IC testing device used in the manufacturing stage of semiconductor integrated circuits (ICs), and particularly relates to an IC testing device used in the manufacturing stage of semiconductor integrated circuits (ICs). The present invention relates to a test device for simultaneously testing each IC in a state in which the ICs are simultaneously tested.

[Technical background of the invention]

For example, the central processing unit (CP) of a microcombinator
When manufacturing ICs for TJ), the above ICs are
When performing functional tests on ICs having dual in-line packages (DIPs), measurement techniques or methods for ICs having dual in-line packages (DIPs) are becoming increasingly streamlined so that multiple ICs can be measured in real time, such as by using the hand 2.

On the other hand, as shown in FIG.
A manufacturing method in which each IC 11 to 14 is measured with the leads 3 formed integrally on the frame 2 and the leads 3 other than specific leads such as those for power supply being cut from the frame 2. In the case of employing the above method, conventionally, a test device is used which sequentially tests a plurality of ICs in the same frame one by one.

Here, an overview of the conventional test device will be explained. In other words, a test pattern having multiple test items for the IC under test is programmed into the test test/e-turn memory, and the test results obtained when a standard, normal IC is tested according to the test pattern described above.・Program the Guturn (which becomes the standard Guturn) into the standard/pattern memory. Then, the test pattern inputted from the test pattern memory is compared with the stored standard pattern and pattern, and based on the comparison result, it is determined whether the test IC is good or bad. Ta.

Note that the conventional test equipment described above requires the standard pattern to be programmed into the memory in advance, so the 76l:
7g operation takes time. Therefore, in order to avoid the above-mentioned time and effort, the test I
A test device improved to use a standard sample IC having the same configuration as C was patented in 1982 by the applicant. 3 3 3 7 0 is proposed.

That is, this test device simultaneously tests a test IC and a standard sample IC according to a common test pattern. 2 above for each test item of e-turn
This method is characterized in that the test results of each IC are compared, and based on the comparison results, it is determined whether the test IC is acceptable or not.

[Problems with background technology]

However, multiple test ICs in the same frame as described above
Sequentially testing one by one increases the testing time and reduces production efficiency. In addition, it is possible to streamline the measurement work by using a handler, but since a flat package IC has multiple leads protruding from each of the four sides, there are many problems in implementing the handler, making it difficult to implement. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is an integrated system that can simultaneously test multiple ICs fixed on the same frame and improve production efficiency by shortening the test time required in IC production. The present invention provides circuit testing equipment.

[Summary of the invention]

That is, the test device of the present invention sequentially checks whether or not each integrated circuit under test has reached a predetermined output state by applying a predetermined input to a plurality of integrated circuits under test fixed on the same frame. After checking the synchronization state of the integrated circuits under test, apply the same test input turn to each of the above integrated circuits at the same time, and compare the test output data of each integrated circuit under test with the reference value. It is characterized in that it determines the quality of the product.

Therefore, it is possible to simultaneously test a plurality of integrated circuits under test fixed to the same frame, reducing the test time required for producing integrated circuits and improving production efficiency.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a test device for simultaneously testing four test ICs 11 to 14 and standard sample ICIo formed on the same frame as shown in FIG. 1 by setting them in corresponding measurement sockets. This shows that. below,
The parts of the apparatus shown in FIG. 2 that are directly related to the present invention will be explained. 11 is an input test pattern memory storing test data k having test data of a plurality of test items, 12 is an interface for the memory 11, and 13 is a timing selector to which initial timing is given from the trigger initialization circuit 14. The input test A-turn memory 11 performs timing processing on the data read out from the input test A-turn memory 11 (inputs a cycle into the data), and trigger detectors 151 to 154 in the test IC unit 8.
give timing.

The input signal turn data which has been subjected to the above-mentioned timing processing is transferred to the driver controller in the above-mentioned test IC unit 8.
Controls 161-164 are given to driver control 165 in pull unit 9. These driver comparators '161 to 165 select the driver mode or the controller mode by the driver selector and Zosta 17, and when in the driver mode, convert the input A turn data into an analog signal and convert the input A turn data into an analog signal to ~14 and ICl- for standard samples
1:). In the controller mode, the function test output signals from each IC 14rIO are converted into digital data (output/turn data) and stored in the output turn data memories 18, 185.

The data stored in the output pattern data memories 181-185 are input to the trigger detectors 151-155 and a digital comparator 20, which will be described later. The trigger detectors 151 to 154 are given timing from the timing selector 13 as described above, and the trigger detector 155 is given initial timing from the trigger initializing circuit 14.

Then, the trigger detectors 151 to 155 sequentially check whether or not the timings of the two manual inputs have been matched (synchronized) by sequence control by the sequence control circuit 19, and transmit the check results to the output A? Turn data memory 18. .about.185 to the digital data gradator 20. This digital comparator 20 receives synchronization check result data from the output A-turn cheater memories 181 to 185 and output nocturne data for each test item, the synchronization check data is sent to the CPU (central processing device) 22,
The output pattern data of each of the test ICs 11 to 14 is compared with the output pattern data of the standard sample IC 10 at the same time, and the comparison result data for each test item is sent to the CPU 22 via the cross line 21. ing.

In addition, 23. -234 are buffer circuits for DC testing of each test IC C-14, 24. ~244 are the test ICs 11~ sent through all of the buffer circuits 231~234.
A/D that converts the DC test output signal (analog signal) of 14 into a digital signal and sends it to the pass line 21
It is a converter.

The CPU 22 determines whether the synchronization check results in each of the trigger detectors 155 to 151VC and the function test results of each test IC C to 14 are acceptable or not based on the data from the A/C comparator 20. D converter 24. Each test IC based on data from ~244
It determines pass or fail of the DC test results from Ha to Ha, sends the determination results to the acceptance box via the operation box interface 25 to display the acceptance or failure of the results, and then connects the PID interface 26 to the acceptance box. The data is then sent to external devices such as a floppy disk device and a typewriter or line printer. The operation of the CPU 22 is based on the program memory (RAM). Test program stored in 7 (including test procedures, DC test reference values, etc.)
Execute based on.

Note that the standard sample IC 10 is compatible with each of the test samples T'
It has exactly the same structure as CJI~14, and has been tested in advance and determined to be a good product.

Further, the input test pattern memory 11 is made up of a RAM, and test data and turn data are given from an external input device before the start of the test.

Next, the operation of the IC testing apparatus having the above configuration will be explained.

(1) Synchronization check of each IC.

First, the timing selector 13 is controlled by the trigger initialization circuit 14, and the timing selector 13
The input nosoturn data for synchronization check from the ICs 16 and 165 are converted into analog signals by the driver comparators 16 and 165, respectively, and supplied to each of the test ICs 21 to 14 and the standard sample IC 10. At this time, each IC
The output signal of a specific external bin of the bar 1410 is used for the same check, and each output signal is converted into output noya turn data by the driver/controller and rake 161 to 165, respectively, and output/setan data. It is stored in memories 181-185. Then, to control the 7th control circuit 19, first, in the trigger detector 155, the initial timing and output /? given from the trigger initialization circuit 14 are determined. Synchronization with the data input from the turn data memory 185 is checked and checked, and the check result is sent to the digital comparator 20 via the output and turn data memory 185.

Next, the sequence control circuit 19 controls the trigger detectors 151 to 154 in the order (note that this order is not particularly limited), and the test ICs 1 to 14 are controlled in the same manner as the standard sample IC 10 described above. The synchronization between the data from each output turn data memory 181 to 184 and the timing of the timing selector 13 is checked, and each check result is output to the output nocturn data memory 181 to IFI4f: via the digital converter 20.
sent to. If the synchronization is achieved through the synchronization check, it means that the standard sample C1o, each sample IcII-14, and the input test pattern memory 11 are synchronized, and a functional test can be performed.

On the other hand, if even one of the test ICs is out of synchronization, CP#22 detects a synchronization error.

(2) Conducting the test.

First, input pattern data for a certain test item is sent from the timing selector 13 to each driver/comparator 16. ~
165, where they are respectively converted into analog signals and supplied to each of ICs HA to HA and 10 at the same time. At this time, each IC bar ~14 and 10 generates a test output signal, and this output signal is transmitted to each driver comparator 16.
, to 165, and are converted into digital signals and stored in output pattern data memories 181 to 185. and,
In the digital comparator 20, the standard sample IC
The stored data from the output 4-turn data memory 18s for IC 10 and each stored data from the output 4-turn data memory 18, 184 for test ICs 11 to 14 are simultaneously compared, and each comparison result is sent to the CPU 22. sent to. Thereafter, tests for each test item are sequentially executed in the same manner as above.

In addition, during the DC test of each sample IO C to 14, each I
ce, ~14 output signals are sent to the DC test buffer circuit 23.
1-234f: A/D converter 241-2 via
44, where the A/D converted data is compared with base rate data by the CPU 22, thereby determining whether the test result is acceptable or not.

(3) Judgment of test results and output of judgment results.

The CPU 22 is connected to each test IC 11 to 1 for each test item.
The quality of each test IC 11 to 14 is comprehensively determined based on the test result data of No. 4, and the determination result is output to an external output device.

Through the series of operations (]) to (3) as described above,
The four test ICs H~14 formed on the same frame were tested at the same time, and after the test was completed, the frame was separated from the measurement socket of the test device and placed on another frame again. The test ICs are set in the measurement socket section, and the same simultaneous test as described above is performed again.

In addition, by testing the four test ICs 11 to 14 as described above at the same time, the test ICs 1 to 1 can be tested as described above.
Roughly speaking, the test time can be reduced to 100% compared to the case where 4 is tested one by one. Strictly speaking, however, during a functional test, it takes time to sequentially synchronize all ICJs, 14 and 10, so the test time is short and the line movement becomes approximately noisy. In addition, during the DC test, each test ICJ
The output signals of I to 14 are each converted into i A/D and sent to the CPU.
Since it takes time to compare the data for 22 seconds, the time saving effect is only approximate.

〔Effect of the invention〕

As described above, according to the IC testing apparatus of the present invention, a plurality of IC's fixed to the same frame can be tested simultaneously, and production efficiency can be improved by shortening the test time required in IC production. .

[Brief explanation of drawings]

FIG. 1 shows the device of the present invention, l:! Figure 2 is a configuration explanatory diagram showing an embodiment of an IC testing apparatus according to the invention. 1, ~14... Test IC, 10... Standard sample IC, 11... Input test board and turn memory, 13.
...Timing selector, 14...Trigger initialization circuit, 151-155...Trigger detector, 16
1-165...driver comparator, 181-1
85...Output) Mother turn data memory, 19...Sequence control circuit, 20...Digital controller, 21...Pass line 1.22...CPU
, 231-234... 1 Free current/test buffer circuit, 241-244... A/D converter.

Claims (3)

[Claims] (1) A synchronization check means that applies a predetermined input to a plurality of integrated circuits under test fixed in the same frame and sequentially checks whether each integrated circuit under test has reached a predetermined output state; and this synchronization check means. After checking the synchronization state of each integrated circuit under test, the same test input data is given to each integrated circuit under test at the same time, and the test output data of each integrated circuit under test is compared with the reference value. 1. An integrated circuit testing device comprising: functional test circuit means for determining the acceptability of a test integrated circuit. (2) The synchronization check means also checks whether synchronization has been achieved with a good standard sample integrated circuit having the same configuration as the test integrated circuit, and the function test circuit means The integrated circuit according to claim 1, characterized in that all test output data obtained by simultaneously applying the same test input data to the integrated circuit under test is used as the reference value. Circuit testing equipment. (3) The functional test circuit means is provided corresponding to an input pattern memory storing test data of a plurality of test items, and each of the test integrated circuits, and is provided with the input A? The input pattern data read out from the pattern memory at a predetermined timing is converted into an analog signal and sent to the integrated circuit under test, and the test output signal from the integrated circuit under test is received and converted into output pattern data. A driver/comparator, a plurality of output/turn data memories provided corresponding to the driver/comparators and storing output digital data of the driver/comparators, and storing data of each output pattern memory as the reference value. Patent Enclosure No. 1, characterized in that the device comprises a digital comparator for comparison, a central processing unit for determining the quality of the test results of each of the integrated circuits under test based on the comparison output of the digital comparator, and a metal fitting. Integrated circuit testing equipment.