JPS59723A - Control system of input and output interface - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an input/output interface control scheme between channels and input/output devices.

Prior Art In the prior art, low-speed input/output devices (IO) such as line printers (LP) and card readers (CR) are connected to byte multiplexer channels (BYMPXCH), and magnetic disk devices (DISK) and magnetic tape devices ( For high-speed IO such as MT), block multiplexer channel (BL
MPXCH), and the data transfer protocol of the IO interface (IF) was determined depending on the type of channel (CH). However, recently, there has been an increase in the speed of 0 work.

From the perspective of relaxing restrictions on IOIF cable length, BLMPXC
In the ``0'' connected to the ``H'', there appears a device 0 that supports a plurality of data transfer protocols and switches between them according to the operation.

Therefore, the same CH has different data transfer protocols.
It has become necessary to connect 0 in series. However, conventional C
H could not support these.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the problems of the prior art and to make it possible to serially connect logs with different data transfer protocols to the same 0H. Also, for each 10 pieces of CH hardware, B Y M P
In the present invention, the CH is stored for each CH type and the data transfer protocol 710 used.

On the other hand, (2) 0 selects and switches the data transfer protocol control circuit according to the data transfer protocol control circuit to be used and the operation. As a result, the 10IP data transfer protocol can be switched depending on the 10 types connected and the executed command.

Embodiments of the Invention An embodiment of the present invention will be explained with reference to FIGS. 1 to 5. 1st
The figure shows the overall configuration of the data processing device. IO6 to IO9 are connected to each of CH4 via Ichiyanagi quasi-IOIFs. Each of CH4 is connected to a channel controller @ (CI-
30) 3. Arithmetic processing unit fk, under the control of (BPU) 2, controls data transfer between main storage device (MS) 1 and IOs 6 to 9. The standard 10IF5 consists of a control signal line and a data line, and by the combined response of these signals, ■06
-9 selection, startup instructions, data transfer, IO status reporting, and other sequences are controlled. Data transfer protocols include low-speed LP and CR#Y connections and byte multiplexing (IOIFv each process 0 uses data in bytes in a time-sharing manner), and high-speed IOi connections such as DISK. Block multiflexing (IO
IFv (each ICI uses data sound blocks on a time-division basis).

Traditionally, CH4
As B Y to control byte multiplexing
Separate CHs were designed, such as M P Faster IO data transfer, l0IF
In view of the relaxation of cable length restrictions in 5, the data transfer protocol for BLMPXCH is also as shown in Figure 2.

There are protocols that use a response format for control signals (hereinafter referred to as normal protocols) and protocols that support high-speed transfer without a response format as shown in FIG. 6 (hereinafter referred to as high-speed protocols).

Switching control of these protocols will be described next.

FIG. 4 shows a main functional diagram of CHCs, CH4, and IOs. CHC3 centrally controls multiple CH4Y. The contents (microprogram) of the control memory 11 (hereinafter referred to as C8) are sequentially read to the control memory register 12 under the control of the control memory control circuit 100 to control the local memory address 16, local memory 14, arithmetic unit 15, etc. are doing.

The decoding circuit 17 decodes the contents of the control storage register 12 and controls the setting and resetting of the registers in CHC3 and CH4. The C)l-IO address holding circuit 16 is located in the CHC3 and is used for C)l and ■0 during execution.
holds the address of These addresses are
In addition to the selection of 4, CH40 control information sent to the local storage address 13 and held in the local storage 14, IO6
It is used as a read/write address for control information of 9 to 9. The local memory 14 has control information (hereinafter referred to as IOW) that holds the CH type and IO type corresponding to each work 0 address.

) is also held. FIG. 5 shows an example of IOW.

The CH4 has a CH type register 18 and an IO type register 19 for storing l0Wv corresponding to the active CH and IO read out from the local storage 14j under the control of a microinstruction. The normal protocol control circuit 20 and the high speed protocol control circuit 21 are circuits that control the corresponding data transfer protocol in the 10IF5.

The 10IF control circuit 22 is a circuit that also has a function of decoding the protocol specification specified by the 10IF5 signal line. The CH switching circuit 23 has a CH type register 18.10.
Type register 19. The normal protocol control circuit 20 and the high speed protocol control circuit 21 are switched based on the output of the l0IF control circuit 22.

Like -CH4, IO8 also has an IO normal protocol control circuit 25 and a high-speed protocol control circuit 26, and depending on the output of the protocol control circuit 27 (the protocol to be used is switched depending on the command to be executed and the content of the operation). 10 switching circuit 24,
Controls IF5.

Next, the operation will be explained. The local memory 14 is connected in advance and stores IOW'Y corresponding to the masonry type 00. In the microprogram, before starting from 06 to 9, the local memory 14 stores CH and IO held in the CH/10 address holding circuit 16.
Read W and sector into CH type register 1s-IO type register 19. When a start instruction is issued from CHC3 to Cl-14, CH4 activates l0IF' control circuit 2.
2 activates IO8 via 10IF5. I (J8 responds with the I OI P control circuit 28. If this startup is successful, data 7 transfer is started. Data transfer is 10 (S ~ 9 of 8 RV I
It is initiated by the N or DATIN signal (see Figure 2). The IO8 holds the command sent through 10IF5'Y in the protocol control circuit 27, and when using the high-speed data transfer protocol, selects the high-speed protocol control circuit 26 and starts data service from DATIN. Cl-14 selects the high-speed protocol control circuit 21 with the CB switching circuit 23 when the l0IF control circuit 22 receives the DATIN signal first and the IO type register 19 specifies the high-speed protocol, and the high-speed protocol is used for l0IF5. control.

This state continues until the data transfer is completed and the next new command is issued. When the operation of IO8 is completed and data transfer is to be performed next with IO9, similarly, IOW corresponding to IO9 is read out and l0IF5 is controlled.

Effects of the Invention According to the present invention, it becomes possible to serially connect devices 0 with different data transfer protocols to one C) and to request data transfer using different protocols in each C). Also C
Depending on the data transfer protocol, it is not necessary to use BYMPX mode or BLMPX mode separately, and by changing the contents of one local memory, any process can be applied to any CH.
It becomes possible to connect at will.

[Brief explanation of drawings]

Fig. 1 shows the overall configuration of the data processing device, Fig. 2 shows an example of a normal data transfer protocol, Fig. 3 shows an example of a high-speed data transfer protocol, and Fig. 4 shows related information. C) A block diagram of IO, the fifth factor is a diagram showing an example of the format of control information (IOW). 1...MS 2...BPU3...
CHC4...CH 51,■OIF 6-9...l010...Control memory control circuit 11...C♂12...Control memory register 13...Local memory address 14...Local memory 1
5... Arithmetic unit 16... CH@IO address holding circuit 17... Decode circuit 18... CH type register 19... IO type register 20... Normal protocol control circuit 21... High speed protocol control Circuit 22, . . , 10IP control circuit 23 . . . CH switching circuit 24 . . 0 switching circuit 25 . . . Normal protocol control circuit 26 . OIF control circuit

Claims (1)

[Claims] The channel is provided with means for storing the data transfer protocol type and channel type for each connected input/output device, means for controlling various data transfer protocols, and means for switching data transfer protocol control, and The input/output device is provided with means for controlling various data transfer protocols and means for switching data transfer protocol control, so that the data transfer protocol can be switched depending on the type of input/output device connected or the command to be executed. A unique input/output interface control method.