JPS598070A - Memory access circuit - Google Patents

Abstract

PURPOSE:To increase the number of bytes of a memory region where a CPU can be applied with simplification of the program constitution and at the same time to improve both data transfer capacity and performance of a system, by adding one comparator and one logical circuit. CONSTITUTION:A lower 8-bit address signal 4 and an upper 7-bit address signal 5 of a general-purpose 16-bit CPU 1 are applied to the input groups of a memory address feeder 2. At the same time, an input/output operation cycle signal 10 is applied to 1-bit 6 of the input terminal group. An access is given to a 64K-RAM memory group 3 with a memory address signal 8 given from the feeder 2. A comparator 11 and a logical discriminating circuit 12 are provided to a memory access circuit. Then a 6-bit address signal 13 of the highest side is applied to the comparator 11, and an output signal 14 of the comparator 11 is applied to the input terminal C of the circuit 12. Then memory operation cycle signals 7 and 10 are supplied to other input terminals A and B of the circuit 12. The output of the circuit 12 is applied to a memory part 3. This increases a memory region where the CPU 1 can be applied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a general-purpose 16-bit microprocessor having data transfer functions in 8-bit and 16-bit units and 16 address lines, and 16 or more 64-kilobyt dynamic RAMs. The present invention relates to a memory access circuit comprised of a group of memories.

As a memory circuit element using a general-purpose 16-bit microprocessor as a CPU, many dynamic RAMs, which have a larger capacity and better mounting efficiency than static RAMs, are being used. If the entire directly addressable capacity of the CPU is used as internal memory, 64 kilobit dynamic RAM (hereinafter referred to as 64 kilobit dynamic RAM), which has the same size but four times the capacity compared to 16 kilobit dynamic RAM, is now available.
Now that 4KD-RAM (hereinafter referred to as 64KD-RAM) can be used, it is effective to use a 64KD-RAM memory configuration in order to downsize the device.

A conventional memory access circuit using 64KD-RAM is shown in FIG. That is, one input group of the 8-bit memory address provider 2 has a general-purpose 16-bit CP.
The lower 8-bit address signal 4 excluding the lowest 1 bit of U1 is input to the other input group, and the upper 7-bit address signal 5 is input to the other input group.
is connected and input 1 bit 6 is grounded. General purpose 1
6 bits) The lowest bit address signal of CPU1 is 64K
It is used as one of the input signals of the data write signal generation circuit for the D-RAM memory group 6. The memory operation cycle coefficient 7 of the general-purpose 16-bit CPU 1 is still 64KD.
- connected to the row address selection terminal 9 of the RAM memory group 6; At the time of memory access, the lower 8-bit address signal 4 is first given as the row address as the address signal 8 for a group of memories, then the upper 7-bit address signal 5 and ground (the word is given as the address signal for a group of memories) as the column address. 8 as j:j choose 1 and 6
4 K, D - Access RAM. However, general purpose 1
The 6-piso hCPU1 is able to perform memory access in 8-bit units (bytes) by allocating 16 address lines with each byte as one address, so even at the maximum memory address, the row address is FFH and the column address is 7FI. (Thus, the address in the column address range 80n=FFH of the 64KD-RAM itself could not be accessed.

As mentioned above, a memory access circuit using a conventional general-purpose 16-bit microprocessor as a CPU has a total of 64Kr.
) - uses 16 RAM,! =, memory capacity 6
Even though it is 4 words (128 bytes), the CPU is actually accessing 64 bytes,
The remaining 64 and 31 bytes were wasted due to a system that processes a large amount of data compared to the program storage,
It is necessary to prepare a preliminary calculation using reference data, etc. one after another.In the case that there is no more data than can be accommodated in the memory capacity of d, 64 bytes, in order to make up for the lack of memory capacity, a certain amount of data must be calculated. Each process requires operations such as transferring the processing results to a floppy disk and reading reference data from the floppy disk for use, especially in systems that require real-time processing of data.
This operation time is a great burden and has the drawback of hindering the improvement of system performance.

The present invention solves the above-mentioned problems and provides a memory access circuit that improves the data processing capacity and performance of the system by effectively utilizing the memory capacity that was previously unused. An embodiment of the present invention will be described below with reference to FIG. Components that are the same as those shown in FIG. 1 will be described with the same reference numerals.

FIG. 2 is a circuit diagram showing one embodiment of a memory circuit according to the present invention. General-purpose 16-bit) The lower 8-bit address signal 4 excluding the least significant bit of the address line of the CPU 1 is connected to one input group of the 8-bit memory address supplier 2, and the other input group is connected to the general-purpose 16-bit CPU.
The upper 7-bit address signal 5 of the address line 1 and the input/output operation cycle signal 7 of the general-purpose 16-bit CPU 1 are connected. Depending on the switching polarity of the memory address supplier 2, the lower 8-bit address signal 4 appears at its output when a memory column address is supplied, and the upper 7-bit address signal 5 and the input/output operation cycle signal 7 appear when a memory column address is supplied. Wanete stipulates the designated address of the memory group B. Here, the input/output operation cycle signal 7 is the general purpose 16
When the bit cPU1 is in the input/output operation cycle state, it shows a logic level 1 (7), and when it is not in a fidget state, it shows a logic level O (d). The first and other input groups connected to the 6-bit address signal 1 are grounded, and when the two input groups match as an output signal 14, the logic level 0 is changed. Logic judgment circuit 12 pieces, 5 input terminals (
A, B, C), 1 is the memory operation cycle signal 7 which becomes a logic level 0 only during the memory operation cycle to the A input terminal, the input/output operation cycle signal 7 is the input/output operation cycle signal 7 to the B input terminal, and the C input The output signal 14 of the comparator 11 is connected to the terminal.
A and B are connected to the output of the logic judgment circuit 12 connected to the row address selection terminal 9 of the memory group 6.

Logic level 0 appears only when the C input terminal is (0, X, X) or (1, 1, 1) (note, the X symbol...
・or 0...). Threading, general purpose 16 bit) C
When the PU 1 is in the memory operation cycle state, the memory group 6 is always accessible, and when it is in the input/output operation cycle state, it is accessible with restrictions placed on the input/output address range.

As mentioned above, when the general-purpose 16-bit) CPU1 is in the memory operation cycle, the row address is variable from 0 to FF"H and the column address is variable from 0 to 7FH, so there are 64 bytes (0
~7FFFH words) can be accessed. General purpose 16-bit) When CPU1 is in the input/output operation cycle, the row address is D to FFH.

The column address is variable from 80H to FFH, but depending on the control of the comparator 11, the column address is 80H.

When 81H, row address selection terminal 9 of memory group 6
Give a non-selection signal to This is to allocate input/output addresses in this range to the input/output ports required externally by the general-purpose 16-bit. Soha, late general purpose 16) CPU1
For a group of memories, the capacity that can be accessed by memory operation commands is 64 bytes, and the capacity that can be accessed by input/output operation commands is 65 bytes, and the capacity of 127 Kbytes can be accessed by normal memory operations or input/output operations. can.

Details 2 As explained above, according to the present invention, one comparator and one logic circuit are added compared to the conventional one, and C
The memory area that can be used by the PU has increased to approximately 64 bytes, and data transfer with this increased memory area is still limited to the CP.
This can be executed using the normal input/output commands of the U, and has the effect of simplifying the program configuration and improving the performance of the system.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional memory access circuit.
FIG. 2 is a circuit diagram showing one embodiment of a memory access circuit according to the present invention. 16-bit CPU using 17/2 Memory address supply device 6, 64KD-RAM memory group 4...lower 8-bit address signal 5, upper 7-bit address signal 6, 1 bit of input terminal group 7, memory operation cycle signal 8... Memory address signal 9, row address selection terminal 10, input/output operation cycle signal 11... comparator 12 logic judgment circuit 13
...Most significant side 6-bit address signal 14 Comparator output signal Patent applicant NEC Corporation Representative Patent attorney Nakai Kanno

Claims (1)

[Claims] (1) A memory access circuit consisting of a general-purpose 16-bit microprocessor with data transfer functions in 8-bit and 16-bit units and 16 address lines, and a memory group consisting of 16 or more 64-kilobit dynamic RAMs. The microprocessor has a memory address supply device, a comparator of 6 bits or more, and a logic judgment circuit of 6 or more human power, and the lower 8 bits excluding the least significant bit of the address line of the microprocessor are connected to one side of the memory address supply device. At the same time, the remaining 7 bits and the input/output operation cycle signal, which is the output signal of the microprocessor, are connected to the other input terminal group of the memory address supplier, and one input terminal group of the comparator. Connect the upper few bits of the address line of the microprocessor to the input terminal group of the logic judgment circuit, and compare the input/output operation cycle signal, which is the output signal of the microprocessor, and the memory operation cycle signal output by the microprocessor, to the input terminal group of the logic judgment circuit. 1. A memory access circuit characterized in that the output signal of the logic determination circuit is connected to the row address selection terminal of the memory group.