JPS5980949A - Resin-encapsulated semiconductor device - Google Patents

Resin-encapsulated semiconductor device

Info

Publication number
JPS5980949A
JPS5980949A JP58118320A JP11832083A JPS5980949A JP S5980949 A JPS5980949 A JP S5980949A JP 58118320 A JP58118320 A JP 58118320A JP 11832083 A JP11832083 A JP 11832083A JP S5980949 A JPS5980949 A JP S5980949A
Authority
JP
Japan
Prior art keywords
resin
tab
semiconductor substrate
semiconductor device
corner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58118320A
Other languages
Japanese (ja)
Inventor
Shigeo Amagi
滋夫 天城
Masahiro Kitamura
北村 允宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58118320A priority Critical patent/JPS5980949A/en
Publication of JPS5980949A publication Critical patent/JPS5980949A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/411Chip-supporting parts, e.g. die pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は半導体基板全体を樹脂でモールドしたIC,L
SI等の樹脂封止半導体装置の構造に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention is an IC, L, in which the entire semiconductor substrate is molded with resin.
This relates to the structure of resin-sealed semiconductor devices such as SI.

樹脂でモールドする半導体装置の構造は第1図に示すよ
うになっており、半導体基板2を金属板よりなるタブ3
に固着した状態で樹脂1によりつりんでいる。このモー
ルド樹脂1と半導体基板2、タブ30線膨張係数が異る
ため各構成材には温度変化に伴う熱応力が生じる。ここ
に使用されている金属板製タブ3は第1図に示すリード
4と共に一枚の金属板より型打ち抜き加工により形成さ
れる。このためタブの一方の側の角部には第2図に示す
ように鋭い角のバリ6が残っている。従来技術において
は半導体基板をバリ6が残る面に対し反対側の面に固着
した後、樹脂でモールドしていた。このためタブの周辺
部に高い応力集中が起ることとなり、モールドレジンに
破断個所7が生じ易かった。
The structure of a semiconductor device molded with resin is shown in FIG. 1, in which a semiconductor substrate 2 is placed between a tab 3 made of a metal plate.
It is suspended by resin 1 while being fixed to. Since the mold resin 1, the semiconductor substrate 2, and the tab 30 have different linear expansion coefficients, thermal stress occurs in each component due to temperature changes. The metal plate tab 3 used here is formed by punching a single metal plate together with the lead 4 shown in FIG. For this reason, a sharp burr 6 remains at one corner of the tab as shown in FIG. In the prior art, the semiconductor substrate was fixed to the surface opposite to the surface where the burr 6 remained, and then molded with resin. For this reason, high stress concentration occurred around the tab, and breakage points 7 were likely to occur in the mold resin.

本発明の目的は樹脂でモールドした半導体装置において
モールド樹脂の破壊を防廿することにある。
An object of the present invention is to prevent mold resin from breaking in a semiconductor device molded with resin.

本発明は、樹脂でモールドした半導体装置のタブ近傍に
生じる応力を解析した結果なされたものである。本発明
に従うと、タブの角部に生じる高い応力を低減する手段
として第3図に示すようにタブ3のバリ6のような鋭い
角を周辺に持っタブ面へ半導体基板2が固着される。
The present invention was made as a result of analyzing the stress generated in the vicinity of the tab of a semiconductor device molded with resin. According to the present invention, the semiconductor substrate 2 is fixed to the tab surface with sharp corners such as burrs 6 of the tab 3 around the periphery, as shown in FIG. 3, as a means of reducing the high stress generated at the corners of the tab.

金属板よりタブ3、リードフレーム乞作り出す最も低価
格で量産性の高い加工法は型打ち抜き法である。この加
工法によれば打ち抜かれた板の側面と表面および裏面と
なす角のうち一方はバリ6のような鋭い角となり、他方
は金属の塑性流動に伴い曲面状になる。そこで、この曲
面状になった角ケ半導体基板が固着される面に対して反
対側に位置させれば、応力集中ン低減できる。
The cheapest and most mass-producible processing method for producing tabs and lead frames from metal plates is the die-cutting method. According to this processing method, one of the angles formed between the side surface and the front and back surfaces of the punched plate becomes a sharp corner like a burr 6, and the other becomes a curved surface due to the plastic flow of the metal. Therefore, by positioning the curved square semiconductor substrate on the opposite side to the surface to which it is fixed, the stress concentration can be reduced.

また、バリ6のような鋭い角部な半導体基板が固着され
る側に位置させれば、弾性率が高い半導体装置の近くに
バリ6があるため、バリ6による高い応力集中を防止す
ることができる。このためタブのバリ取り作業、角を丸
める作業が不要となる。
Furthermore, if the burr 6 is located on the side where a semiconductor substrate with a sharp corner is fixed, high stress concentration due to the burr 6 can be prevented since the burr 6 is located near a semiconductor device with a high elastic modulus. can. This eliminates the need for tab deburring and corner rounding.

本発明の実施例を第3図、第4図によって説明する。An embodiment of the present invention will be explained with reference to FIGS. 3 and 4.

半導体基板2はタブ3のバリが出ている側に固着され、
モールド樹脂1によって全体がモールドされている。こ
のタブ3の半導体基板Z固着した面に対して反対側の角
の曲率半径Rは0.02111である。本実施例におけ
るタブの角部の応力と従来品の角部の応力を比較すると
、本実施例の方が従来品より3割近く低減していること
がわかった。
The semiconductor substrate 2 is fixed to the burr side of the tab 3,
The entire body is molded with mold resin 1. The radius of curvature R of the corner of this tab 3 opposite to the surface to which the semiconductor substrate Z is fixed is 0.02111. Comparing the stress at the corner of the tab in this example with the stress at the corner of the conventional product, it was found that the stress in this example was reduced by nearly 30% compared to the conventional product.

本発明によれば半導体装置におけるタブ3の角部に生じ
る応力集中を軽減できるのでモールド樹脂の破壊を防止
できる。第3図に図示のように、タブ3の鋭い角部6が
ある面から樹脂表面までの距離L1が、タブ30反対面
から樹脂表面(裏面)までの距離り、よりも大きい場合
は、半導体装置の信頼度が同上する。すなわち樹脂の応
力集中しやすい部分から樹脂表面までの距離が大きくな
ることによって、万−樹脂中に局部的な破壊が生じたと
しても、その破壊が樹脂表面にまで達することが起りに
くくなる。その結果、封止樹脂外からの汚染に対して半
導体基板を充分に保護できるようKなる。
According to the present invention, it is possible to reduce the concentration of stress occurring at the corners of the tab 3 in the semiconductor device, thereby preventing the mold resin from breaking. As shown in FIG. 3, if the distance L1 from the surface of the tab 3 with the sharp corner 6 to the resin surface is greater than the distance from the opposite surface of the tab 30 to the resin surface (back surface), the semiconductor The reliability of the device is the same as above. That is, by increasing the distance from the part of the resin where stress tends to concentrate to the resin surface, even if a local fracture occurs in the resin, the fracture is less likely to reach the resin surface. As a result, K is set such that the semiconductor substrate can be sufficiently protected from contamination from outside the sealing resin.

また、型打ち抜き加工したタブのバリ取りあるいは角の
丸め作業が不要となる。
Further, there is no need to deburr or round the corners of the punched tab.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は樹脂モールドによりパッケージしたLSIの部
分断面斜視図、第2図は従来品の断面図、第3図は本発
明の実施例の断面図、第4図は本発明の実施例の部分断
面図である。 1・・・モールド樹脂、2・・・半導体基板、3・・・
タブ、4・・・リードフレーム、5・・・引出し線、6
・・・ばり、7・・・破断個所。 第  1  図 グ 第  2 図 第3図 第  4 図
FIG. 1 is a partial cross-sectional perspective view of an LSI packaged by resin molding, FIG. 2 is a cross-sectional view of a conventional product, FIG. 3 is a cross-sectional view of an embodiment of the present invention, and FIG. 4 is a portion of an embodiment of the present invention. FIG. 1...Mold resin, 2...Semiconductor substrate, 3...
Tab, 4...Lead frame, 5...Leader line, 6
...Burr, 7...Broken point. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板を金属板よりなるタブの上に固着し、上
記タブ及び上記半導体基板を樹脂で封止した樹脂封止半
導体装置であって、上記タブはその主面に対してはy直
交する側面と、上記主面と側面との間で鋭い角となる角
部と、上記主面の反対側の面と上記側面との間でゆるい
曲面状にされた角部とを持ち、上記半導体基板は上記主
面に固着されてなることを特徴とする樹脂封止半導体装
置。
1. A resin-sealed semiconductor device in which a semiconductor substrate is fixed onto a tab made of a metal plate, and the tab and the semiconductor substrate are sealed with resin, the tab being y-orthogonal to the main surface thereof. The semiconductor substrate has a side surface, a corner that is a sharp corner between the main surface and the side surface, and a corner that is gently curved between the surface opposite to the main surface and the side surface. is fixed to the main surface.
JP58118320A 1983-07-01 1983-07-01 Resin-encapsulated semiconductor device Pending JPS5980949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58118320A JPS5980949A (en) 1983-07-01 1983-07-01 Resin-encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58118320A JPS5980949A (en) 1983-07-01 1983-07-01 Resin-encapsulated semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP58118319A Division JPS5994449A (en) 1983-07-01 1983-07-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5980949A true JPS5980949A (en) 1984-05-10

Family

ID=14733746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58118320A Pending JPS5980949A (en) 1983-07-01 1983-07-01 Resin-encapsulated semiconductor device

Country Status (1)

Country Link
JP (1) JPS5980949A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016714A (en) * 2006-07-07 2008-01-24 Sanyo Electric Co Ltd Frame package type semiconductor laser device
JP2008016715A (en) * 2006-07-07 2008-01-24 Sanyo Electric Co Ltd Frame package type semiconductor laser device
JP2008021754A (en) * 2006-07-12 2008-01-31 Sanyo Electric Co Ltd Frame package type semiconductor laser device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554985A (en) * 1978-06-27 1980-01-14 Nec Kyushu Ltd Lead frame for semiconductor device
JPS5524694A (en) * 1979-08-09 1980-02-21 Eastman Kodak Co Fluorescent analysis for bilirubin

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554985A (en) * 1978-06-27 1980-01-14 Nec Kyushu Ltd Lead frame for semiconductor device
JPS5524694A (en) * 1979-08-09 1980-02-21 Eastman Kodak Co Fluorescent analysis for bilirubin

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016714A (en) * 2006-07-07 2008-01-24 Sanyo Electric Co Ltd Frame package type semiconductor laser device
JP2008016715A (en) * 2006-07-07 2008-01-24 Sanyo Electric Co Ltd Frame package type semiconductor laser device
JP2008021754A (en) * 2006-07-12 2008-01-31 Sanyo Electric Co Ltd Frame package type semiconductor laser device

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