JPS598427A - Digital-analog conversion circuit and its conversion method - Google Patents

Abstract

PURPOSE:To attain the D/A conversion with decreased distortion factor in high speed, by controlling an integrating time with a timewise weighting for forming a weighted electric quantity. CONSTITUTION:The integrating circuits I1, I2 are connected in cascade and a reference voltage is applied from a reference potential source 19 to the circuit I1. Switches 15, 16, 17, 18 are inserted among a potential source 19 and the circuit I1, I2, and an n-bit digital signal to be converted with latch circuits 23, 24 is split into an optional N-set of groups and stored. A time generating circuit 21 generates the time corresponding to the least significant bit of each group split based on a reference clock pulse CLK. A control circuit 20 generates a weighted electric quantity in the circuits I1, I2 based on the time and controls a switch circuit integrating the electric quantity for the time corresponding to the data value of the group.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D-A conversion circuit and a D-A conversion method for converting a quantized digital signal into an analog signal, and particularly relates to a D-A conversion circuit and a D-A conversion method for converting a quantized digital signal into an analog signal.
), digital audio tape, and other audio equipment, and its purpose is to reduce distortion and speed up operation.

Generally, DAD and digital audio tape have
An analog audio signal is sampled and its quantized digital signal is recorded. For reproduction, the recorded digital signal is extracted and converted into an analog signal.

Conventionally, digital signals are converted into analog signals using ladder-type resistance circuits, etc., to convert weighted electrical quantities,
For example, there is a method of synthesizing current or voltage. A DA converter using this method generates noise when reproducing a very low level signal. That is, when reproducing a small level, the input digital signal is 011.
Because it constantly goes back and forth between ``111'' and ``100...000'', the resistor that generates the weighted amount of electricity switches each time, so the error in that resistor appears as noise. It is. Furthermore, when the number of bits of digital signals increases and high resolution is required, it is necessary to precisely trim individual resistors such as ladder-type resistor circuits and adjust them to accurate values, which requires technology. This has caused high-resolution D-A converters to be expensive.

Furthermore, conventionally, an integral type DA converter is formed as shown in FIG. In FIG. 1, an integrator is formed by an operational amplifier (1), a capacitor (2) and an input resistor (3). A reference potential source (4) is connected to the input resistor (3) via switch means (5), and a capacitor (2)
Switch means (6) are also provided at both ends. The opening and closing of the switch means (51(6)) is controlled by the control circuit (7), and in particular, the closing time of the switch means (5) is determined by the time generating circuit (8) to which a digital signal is applied. It is determined by the time created based on the value of the applied digital signal.That is, first, the switching means (6
), the charge in the capacitor (2) is discharged and the output voltage of the operational amplifier (1) becomes 0 volts. Then, at the same time as the switch means (5) is closed, the time generating circuit (8) counts the clock pulse CLK applied from the outside, and when the count matches the applied digital signal, the time generating circuit (8) counts the clock pulse CLK applied from the outside. ) is played out. Therefore, during its counting time, the integrator uses the reference potential source (
4) is integrated, a voltage proportional to the counting time i is generated at the output of the operational amplifier (1), and JJ, -A
A conversion is made. However, in this integration method, if the resolution of the digital signal is n + v), the maximum
Since one clock pulse is required, the higher the resolution, the longer it takes to obtain an output, resulting in slower operation.

The present invention has been made in view of the above points, and uses a plurality of continuously connected integrating circuits, and also divides the n-bi-lido digital signal to be converted into N groups. For each group, a weighted electrical quantity corresponding to the lowest bi-rid of each group is created by an integrating circuit, and that electrical quantity is further integrated over time corresponding to the data of the corresponding group by an integrating circuit in a subsequent stage. The present invention provides a DA conversion circuit and a DA conversion method for obtaining an analog signal by performing the following steps. Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram showing an embodiment of the present invention. The digital signal to be converted consists of 16 bits D1 to D16, and this digital signal is divided into two groups D1 of 8 bits each. ~D8,09~D1 This is a case that can be divided into B. Integrating circuits 11 and 12 each include an operational amplifier (9
) (10) and the resistance circle (6
), and a capacitor (13) Q41 connected between the - input terminal and the output terminal, and the capacitor (
13) and (14) are provided with switching means (15) and (16) for discharging the accumulated charge.

Integrating circuits 1 and 12 are continuously connected via the switching means (07), and the integrating circuit 11 is connected via the switching means (1).
A reference potential source α9) is connected via 8).

The control circuit (4) includes a time generation circuit (21) and a counter ■
Based on the output of
The opening and closing of the η-scream is controlled according to a predetermined procedure.

The time generating circuit (21) counts the applied reference black riff pulse CLK, and calculates the lowest bi-lid of each group I)1 to D8 and D9 to DI6 of the digital signal divided into two.
That is, times r1 and T2 are created which correspond to Dl and D9 and are weighted at a ratio of 1:2. For example, time T1 corresponds to one clock of the reference clock pulse CLK, and eight T2 corresponds to 28 clock riffs. (23) is a latch circuit that stores the lower 8 bits Di to D8 of the digital signal. Upper 8 bits of digital signal) D9 to D16
The digital signal to be converted is stored by dividing the U-rich circuit into (goods). Further, the digital signals stored in the Usochi circuits (23) and (24) are controlled by the control circuit (2) and are sent to the multiplexer (O) according to a predetermined procedure.
is sent to the counter (22) via the counter (22). Kara/ri□□
□ consists of, for example, a subtraction counter or a counter with -paper detection, and when the applied reference black riff pulse CLK is equal to or counted as the data value represented by the transmitted digital signal, it is sent to the control circuit □. Emits output.

That is, it creates a time corresponding to the data value of the digital signal.

FIG. 6 is a timing diagram showing the operation in the pro-riff diagram shown in FIG. 2, and FIG.
The output voltage V1. FIG. 5(b) shows the output voltage 2 of the integrating circuit I2. The operation of FIG. 2 and the IJ-A conversion method will be explained below based on FIG.

First, the 16-bit digital signals to be converted are D1 to D.
16 is the lower 8 bits, lid l) 1~D8 and the upper 8 bits/v
)99 to D16, each of which has a Sochi circuit (5)
! (24). Next, the control circuit (2Q) closes and opens the bottom of the capacitor (1) from timing [1 to timing L2 (this means α5).
By discharging the charge in step 3), the output voltage ■1 of the integrating circuit ■1 is brought to O■, that is, to the initial state. Then, at timing t2, the switch means 18) is closed, the reference potential source α is connected to the integrating circuit 11, and the time generating circuit (2I) is operated to generate the reference clock pulse CLK.
Count 28 pieces to create time T2. Meanwhile, integrating circuit 1
1 performs an integral operation of the reference potential #0ω, and its output voltage v
1 rises with a slope determined by the resistor (11) and capacitor 03). On the other hand, the control circuit ■ is a time generation circuit (2
Timing t3 before 1) counts 2” CLK
and during the period E4, the sui-rich means 06) is opened and closed,
Integrating circuit (2) is initialized by discharging the capacitor circle.

At timing t5, the time generation circuit (211 to 2
8 When the output indicating the end of cUK counting is made, the control circuit (■) opens the switch means 08 to end the integration operation of the integration circuit 11, and at the same time opens the switch means (17).
) is closed and the output voltage of the integrating circuit 11 is applied to the integrating circuit I2. The output voltage V1 of the integrating circuit 11 at this time is a weighted electric quantity corresponding to the 9th bit (D9) of the digital signal, and this output voltage V1 is applied to the integrating circuit I2 of the digital signals D9 to D16. D/A conversion of the upper 8 bits is performed by integrating the time corresponding to the data value. That is, at timing t5, U-Richi circuit (2)
The digital signals D9 to D16 stored in are applied to the counter □□□ via the multiplexer (5), and the counter counts the same number of reference clock pulses CLK as the applied data value, and for example, at timing t6. and outputs an output indicating the end of counting to the control circuit (2). Then, the control circuit (4) opens the switch means aη, and the integrating circuit 1
Stop the integral operation of step 2. Therefore, the output voltage v2 increased by the integration of the output voltage V1 becomes an analog quantity corresponding to the upper eight bits 1)9 to D16.

Next, the switching means (15) is opened and closed between timings t6 and [7], and when the integration circuit 11 is initialized, that is, at timing t8 after time T1,
Administer Sui Rich Means 08). Therefore, the output voltage {circle around (1)} at this time becomes a weighted electric quantity corresponding to the first bit 01 of the digital signal.

Also, the timing [at 8, Sui-Sochi means 07]
By closing , the integration circuit 2 outputs the electrical quantity corresponding to the upper 8 bits (...)D9 to D16 held by the previous integration operation, and the output weighted corresponding to the first bit. Integrate and add voltage ■1.

At this timing [8], the digital signals 01 to D8 stored in the latch circuit (support) are transferred to the multiplexer (2
5) to the counter (2), and the counter (support) counts the same number of reference clock pulses CLK as the data values of the digital signal L)1 to D8. αη is inserted and the integral operation stops. Therefore, the output power (2) of the integrating circuit 12 at this time is output as an analog signal obtained by converting the digital signals u1 to Du.

In this way, by creating a weighted time corresponding to the lowest Bi-Lid of each group by the time generation circuit (2) and using that time as the integration time of the integrating circuit 11, the lowest Bi-Lid of each group is created. By creating a weighted electrical quantity corresponding to the lower bit, and integrating this electrical quantity in the integrating circuit 12 for a time corresponding to the data value of each group, D-
A conversion is performed. Also, one cycle of D-A conversion is [1 to t9, of which the reference clock riff required for the integration time excluding the extremely short initialization time is 28+1
+lJ1~8+D,~16CLK, maximum is 76
It is 9CLK. On the other hand, according to the conventional integration method shown in FIG.
It becomes necessary. Therefore, the conversion time for one cycle is significantly shortened compared to the conventional one, resulting in a DA converter circuit capable of high-speed operation. Also, sui-rich means Q5)Q6)(1
7) The control circuit (20) that controls (18), the time generation circuit (21), the false circuit (23), (24), the multiplexer (25), and the counter (2) can all be configured by digital circuits, and special This eliminates the need for circuits and analog circuits that require precision, making the circuit easy to integrate.

In the embodiment shown in FIG. 2, the 16-bit digital signals D1 to D16 to be converted are divided into two groups of 8-bit IV to each, but are divided into four groups of 4-bit IV, i.e., J)1~D4.1)5~D8.1]9~I)1
2.1) It can also be divided into 13 to DI6. In this case, the time generating circuit (21)
The time Tj (for example, one CLK) corresponding to the fifth
Time T2 corresponding to bit D5 (for example, 2 CLKs)
, 9th B., )D9 corresponds to the time T3 (for example, CL
K2” pieces) and the time T corresponding to the 13th bi-rid D13
4 (for example, 212 CLKs),
Further, the latch circuits (to) (24) are four latch circuits each composed of 4 bits. Then, for each group, the integration circuit 11 performs a time T1. T2. T3. Create a weighted quantity of electricity based on T4, and integrate the quantity of electricity with an integrator circuit■
1) -A conversion is performed by integrating the time corresponding to the data value of the group in step 2 and adding the results. Also, when dividing into three groups, D1 to D
s s 1) 6-D10. Even if the numbers of D11 to D16 (, B of each group, etc.) are different, use the same procedure to D.
-A can be converted.

In addition, the Swiss-Sochi means σ5) (16) shown in this example
(17) Q8) is composed of an electronic switch such as an analog switch using a C-MOS transistor.

As described above, according to the present invention, by taking advantage of the feature of the integration method, that is, its excellent linearity, and further controlling the integration time by temporal weighting to create a weighted electric quantity, A D-A conversion circuit with a reduced distortion factor can be obtained, and by dividing an n-bit digital signal into arbitrary groups consisting of an arbitrary number of bits and performing conversion for each group, it is possible to achieve high resolution. Even in such cases, the conversion time can be shortened and high-speed operation can be performed. Furthermore, there is also the advantage that no special circuit is required, making it easier to integrate the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a pro-riff diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram explaining the operation of the pro-riff diagram shown in FIG. be. (9) α0)...Operational amplifier, 0 plate...Resistance, Q3
1 (141... capacitor, (15) (16) (17
)Q8+...Suitable means, (19)...Reference potential source, (20)...Control circuit, (21)...Time generating circuit, (support)...Counter (23)( Goods)...Sochi circuit, jealousy)...Multiplexer. Figure 1 Figure 2 “゛””°Communication 1
Figure 8 11

Claims (2)

[Claims] (1) An integrating circuit that is continuously connected in multiple stages, a reference potential source for applying a reference voltage to the first stage of the integrating circuit, a switch interposed between the reference potential source and the first stage integrating circuit, and each integrating circuit.・Sochi means, a storage circuit that divides and stores the n biv) digital signals to be converted into N arbitrary groups;
a time generation circuit that generates a time corresponding to the least significant bit of each of the divided groups using a reference clock pulse; and a time generation circuit that generates a time corresponding to the least significant bit of each divided group; and a weighted electrical quantity to the predetermined integration circuit based on the time generated by the time generation circuit. and a control circuit for controlling the Swiss/Sochi means so as to generate and integrate the weighted electrical quantity for a time corresponding to the data value of the group. (2) Divide the digital signal consisting of n bits to be converted into an analog signal into N groups, and apply the weighted electrical quantity corresponding to the lowest bit of each group to the continuously connected integrating circuit. For each group, generate electricity at a predetermined stage, integrate the amount of electricity at the predetermined stage in an integrating circuit at the subsequent stage for a time based on the data value of that group, and hold the amount of electricity in the integrating circuit at the final stage. D-
A conversion method.