JPS5984331A - Device for automatically adjusting azimuth of reproducing head - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and reduce the cost of the titled device, by changing the azimuth of a reproducing head in response to the advance and delay of the phase of a signal and the high and low levels of an inversion signal in the direction, in which the phases of the 1st and the 2nd phase comparison signals coincide with each other. CONSTITUTION:When the azimuth of a reproducing head 1 is not under an appropriate condition and the phase of one side phase comparison signal advances than that of the other side phase comparison signal, the level of an inversion signal at the output point O1 of a phase comparison circuit 8 becomes high level Va by a high-level signal from the output terminal Q1 of a flip-flop circuit FF1. When the level becomes high, a dead zone setting circuit 15 outputs a high- level signal and closes the analog switches SW1 and SW2 of a switching circuit 16. In response to the closing of the high level Vb of an inversion signal is inputted into the switching circuit 16 and the azimuth of the reproducing head 1 is changed in the direction, in which the phases of the 1st and the 2nd phase comparison signals coincide with each other. When such an arrangement is made, the circuit constitution can be simplified and the cost can be reduced.

Description

[Detailed description of the invention]

The present invention relates to an improvement in a magnetic recording/reproducing device, particularly an automatic azimuth adjustment device for a 70P4 raw head. For example, if the azimuth of the playback head is not appropriate, a phase shift will occur between the playback signals from the left and right recording tracks, and the playback characteristics in the city area will deteriorate. In order to solve this problem, a device for adjusting the azimuth of the playback head by 1'' using the recording signal has been proposed, for example, in Japanese Patent Application Laid-Open No. 55-14597. The recording track of one channel, for example, the right channel, is divided into an upper half and a lower half by a specially constructed playback head, and the signals are scanned separately, and the amount of phase difference between the playback signals obtained from each is detected.
The azimuth of the reproducing head is automatically adjusted based on this amount of phase difference. However, according to such conventional devices, it is only necessary to detect the amount of phase difference between the reproduced signals, but the amount of phase difference obtained by dividing the recording track of one channel into upper and lower sections and detecting it is If the azimuth of the reproducing head was to be adjusted by a feedback control system based on this, the circuit configuration of this control system would have to be very complicated, which would be difficult to realize in practice. From a cost perspective, practicality is also an issue. The present invention has been made in order to improve the problems of such conventional devices. Compare the phases of the two phase comparison signals, and obtain an inverted signal 7 which is inverted to a crystal level and a ward level in response to the lead or lag of one phase relative to the other, and adjust the azimuth of the reproducing head by this inverted signal. It is an appendix that it is configured as follows. The embodiment shown in the drawings below? Referring to explanation 1 of the present invention, in FIG. The recorded sound (CT number, for example, is divided into the upper and lower parts and scanned, and the playback signals 8a and 8 are sent to the respective coils a and b.
1). Composite signal of endogenous signals Sa + Sb
1. is the right channel playback signal played by a normal playback head, and is shown from output terminal 0 as audio 6 output No. 3. [One voice is sent to the writing circuit. In addition, the 1 composite sign Sa + Sb and the signal Sb are used as azimuth adjustment signals, and after being made into signals of the same level by amplifiers 2 and 3, they are sent to the 3rd band III overfilter 4.
. The positive components of each rectangular wave signal passing through the diode DI+1)2 are input to the phase comparison circuit 8 as a phase comparison signal. The phase comparison circuit 8 compares the phases of the inner phase comparison signals,
In response to the phase lead and lag of one with respect to the other, a level state is generated at output point 01 of the inverted signal which inverts to level Va, or low level 0. The phase comparison circuit 8 includes a D-type flip-flop circuit 12F1 and a NOR circuit N.
The flip-flop circuit FF1 is a data terminal to which the output of the waveform conversion circuit 7 is inputted via the diode 1)1). A clock terminal CL1 to which the output of the waveform conversion circuit 6 is input via a diode D2'l, a reset terminal R1, an output terminal Q1, an inverted output terminal Q1. and a grounded set terminal S1. The output terminal Q1 is directly connected to the output point 01 via the diode D3'it, and the inverted output terminal Q1 is connected to the single input terminal of the NOR circuit NOH. The reset terminal I (1 and the input of the other output of the NOR circuit NOH are respectively described later) is connected to the output terminal Qz and the inverted output terminal Q2 of the flip-flop circuit Fit2. The level detection circuit 12 enables the phase comparator circuit 8 to operate when the reproduction head 1 is reproducing the audio signal, that is, when the level of the reproduction signal is equal to or higher than a predetermined value. In response to the presence/absence of the dead zone setting circuit 1,
5, the detection sensitivity is increased and decreased 7 times. Level detection circuit 12 B) - flip-flop circuit F2
The positive component of the combined output is given to the 1st node I (2 is the band pass filter 4, 5σ) output, and both the data terminal D2 and the clock terminal CL2 are It is grounded, and its set terminal S2 is connected to the power supply +Vcc (・
Ru. Here, IJ type flip-flop circuit FFJ and 1;
``F2 is commercially available from Tokyo Shibaura Kamekiki 1)U A Ll)-'r'yPEFl, IP Fl
, UP (Product) No. Tc4013BP) is preferably used. The time constant' circuit 14 includes resistors IL1, Ih + R3,
Capacitor C1, diode D5 color pl, +
Diode D5 responds to the output state of output terminal Q2 of
and the charging current of capacitor CI via resistor R2 or resistor R
1 and R3, and the constants of each resistor and capacitor are set so that the charging time is short and the discharging time is long. The detection sensitivity switching circuit 13 is a switching transistor Tr.
1. Diode D6. Nand circuit N, capacitor C2,
C3 and resistance n4. The resistor R5 and the capacitor C3, which are connected between the output point 01 of the comparator circuit 8 and the ground, constitute a first integrating circuit that obtains the integral information of the inverted signal. The additional zone setting circuit 15 is a transistor "r2".
y ”r3 t Tr4 - consists of a width comparator/wind circuit consisting of diode D7, etc., and the reference power supply +v
Compare the reference level vb supplied from b to the base of the transistor Tr4 with the integrated output of the first integrating circuit, and if the integrated output level is not within the dead zone level with respect to the reference level vb, the output level is high. Analog switch sW1 of the switch circuit 16 which outputs a level signal and will be described later
, SW2 is set to lVJ, and when it enters the dead zone level of the gate, it outputs a low level signal and opens these switches f. Note that the dead zone level in this embodiment is the transistor Illr2 to Tr4 and the diode J)7-11.
It is set to vb±1.2 volts depending on the direction. The output point o1 of the phase circuit 8, which is connected to the reference power supply +vb via the resistor Ro, is connected to the switch circuit I6.The capacitor c4 is connected between the connection point of the analog switches SW1 and SW2 and the reference power supply +vb. is the resistor R6 and the second
Construct an integrator circuit. Furthermore, the resistor H7 connected in parallel to the capacitor C4 is connected to the analog switch SW1, 8W.
2 is a discharge resistor when it is open. The output of the second integration circuit is supplied to the motor drive circuit 9 when the analog switch 8Wlr, so-called 2, is closed, and the output of the circuit 9 drives and controls the azimuth adjustment motor 10 that changes the azimuth of the reproducing head. Mall drive 9'Q path 9 has operational amplifier 17, transistor URI l1lr5. The output of the second integrating circuit is connected to the four inputs 91' of the operational amplifier 17 whose input terminals are connected to the reference voltage Vb. The direct voltage level is the high level signal 17 output from the above-mentioned D-type flip-flop circuit FFl.
, ) L/bell VavC is set equal and further Tt
The t-pressure levels Va and Vb are set in the relationship Va=2Vb. In addition, the analog switch 8W1°8 of the switch circuit 16
When W2 is open, one input terminal of the operational amplifier 17 is kept at level yb, and the resistor II8. The resistance values of J (9 are set equal. Figure 2 is an example of the azimuth adjustment mechanism. When the motor rotates, the bell)
c rotates, and the lever 11 d, one end of which meshes with the gear 13 c, rotates around the pivot 11 e, and the link 1
Move wedge 11g through 1f. As a result, the reproducing head 1 rotates around the fulcrum P, and its azimuth changes. In the above configuration, an audio reproduction signal is obtained from the carrier head 1, and the flip-flop circuit Fi of the level detection circuit #S11, +2 reset V+ili terminal 1 (2 to high level 4
When No. 11 is applied, the output states of the output terminal Q2 and the inverted output terminal Q2 of 11'F2 change from the high level and low level states to the concave level and high level states, respectively, and the position ( 1] The input of the flip-flop circuit 1 of the comparison circuit 8 is changed from the high level signal to the low level signal of the reset terminal R1 of F1, and the input of the NOR circuit N (the other side of JR) is changed from the catfish level signal to the Akane level signal. Since Jt changes, the phase comparison signal of one side (manual power of clock terminal CL1) and the other position 411 Higesengo (data terminal ■)
Depending on the phase lead or lag of the 5 inputs), a high L/bell Va is applied to the output terminal Q1 and the inverted output terminal Q of 1) p1.
and U fli L' bevel signals, or 1 degree level and high bevel signals are output. On the other hand, in response to the output change from the high level to the round level at the output terminal Q2 of F[2, the capacitor C1 of the time constant circuit 14 starts discharging via the resistor '3+R1, but the discharging time is set to be long. After this output change, 79r constant time "I'l (for example, 10 se
c) The switching transistors 1' and 1 of the detection sensitivity switching circuit 13 are kept in the ON state until the time period elapses. As a result, the grounding state of the capacitor C2 via the quotient resistor I (4) is maintained, so the detection sensitivity of the dead zone setting circuit 15 remains high. If this is not the case, and the phase of one of the phase comparison signals is ahead of the other, the level of the inverted signal at the output point 01 of the phase comparison circuit 8 will be increased by the high level signal from the output terminal Q1 of the phase comparison circuit 8. As a result, the integrated output level of the 8++1 integrating circuit gradually decreases from the reference level vb, and when it exceeds the dead zone upper limit level Vb + 1.2 volts, the dead zone setting circuit 15 outputs a high level signal. Then, the analog switch 1.SW2 of the switch circuit 16 is closed.In response to this closure, the high level vb of the inverted signal is input to the switch circuit 16, and the second
Since the integrated output of the integrating circuit exceeds the reference level vb,
The azimuth adjustment motor lO starts rotating in one predetermined force direction, and moves the reproducing head l in a direction in which the azimuth is appropriate. Then, when the azimuth of the reproducing head 1 exceeds the proper position and the phase relationship of the phase comparison signal is reversed, the level of the inverted signal is inverted by 1° to a level O. This lowers the output level of the second integrating circuit, and when this falls below the reference level vb, the motor 10 is reversely rotated to return the azimuth of the reproducing head l to the proper position. In this way, the reproducing head 1 vibrates around its proper azimuth position, and its amplitude gradually decreases as the inversion repetition of the inverted signal becomes faster. On the other hand, the output level of the first integrating circuit also increases with the inverted signal. It gradually decreases in response to repeated reversals, and when it enters the dead zone, the dead zone setting circuit 15 outputs a low level signal and opens the analog switches SW and SW2.This causes the motor 10 to stop.
The reproducing head 1 is kept stationary at a substantially appropriate azimuth position. Conversely, when the operation is started with the phase and phase of one phase comparison signal lagging behind the other, the playback head 1 is similarly stopped at approximately the appropriate azimuth position, but in this case, the dead zone Analog switch SWl in relation to lower 1sJ,j rep*Vb-1,2 volts. 5W20 on/off is performed. Such azimuth adjustment is sufficiently completed within the above-mentioned time Tl during which the detection sensitivity is maintained at a high state, and after the sound reproduction signal is detected, the switching transistor Tri of the detection sensitivity switching circuit 13 is turned off when the time TI elapses. However, since capacitor C2 is connected in parallel to capacitor C3, the detection sensitivity of dead zone setting circuit 15 is reduced. This prevents the reproducing head, which has been set to the appropriate azimuth, from moving unnecessarily in response to an exceptional phase shift between the phase comparison signals due to tape bending or the like. ! However, in this state of low detection sensitivity, the level detection circuit 12 does not detect the back door reproduction (g) and is added or subtracted immediately when a high level signal is output from the output terminal Q2 of Fl-2. Since the detection sensitivity is always returned to the normal state at the beginning of the unrecorded part of 1. Even in this case, the azimuth of the playback track is adjusted according to the backdoor playback signal from the recording section at the beginning of the next song. The azimuth of the reproducing head can be automatically adjusted by detecting the lead or lag in the phase of one of the obtained phase comparison signals with respect to the other.Also, the azimuth of the reproducing head can be automatically adjusted without directly moving the motor with the inverted signal.
Since the drive 1" is inputted through the switch circuit 2, there is no need to force the raw head unnecessarily (1) except when adjusting the azimuth, and the high level or low level inverted signal can be connected to the 10 contact signal. Since the input is not input to the motor drive circuit but via the integration circuit, violent rotation of the motor core at the start of adjustment is prevented, and the effect on the raw signal of the audio being extracted at the same time is reduced. Furthermore, Fig. 3 shows another embodiment of the phase comparator circuit.
'li' 3 is its data terminal J, J3, clock driver C

[It is a type 1) type flip-flop circuit in which the phase ratio line signal is inputted to 3, and the outputs from its output terminal Q3 and inverted output terminal Q3 are respectively iil+i phase comparison signal α and level detection circuit] It is input to the NAND circuit "1 t" 2 together with the inverted output of pli' 2, the output of the NAND circuit N1 is passed through the inverter 2 and the diode D8, and the output of the NAND circuit N2 is passed through the diode D9. and are output to output point 03, respectively. Therefore, this output point 03 has high level (repetitive signal of reference level and sieve level) and low level (repetitive signal of reference level and low level) depending on the phase lead and lag of one phase comparison signal with respect to the other. ) is output. Further, the apparatus of the present invention is not limited to the above-described embodiments, and it goes without saying that the width of the dead zone, etc. can be set freely.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of one embodiment of the present invention, FIG. 2 is a diagram showing an example of the azimuth adjustment mechanism used in the present invention, and FIG. 3 is a diagram showing another embodiment 2 of the phase comparator circuit. 1 is a circuit diagram. ■...Playback head, 2, 3...Amplifier, 4, 5...
・Band filter, 6, 7...Waveform conversion circuit, 8...
Phase comparison circuit, 9... Motor drive circuit, 10... Motor, 15... Dead zone setting circuit, 1 (5...
Resistance, C2, C3... Condensation "S."
l:,.・! ,-1) Figure 3

Claims (3)

[Claims] (1) A playback head that divides and plays back the same recording track of a recording deso by 1° in the width direction of the recording track, and a first and second playback head that provides azimuth information of the playback head from the divided playback signals obtained by this divided playback. means for forming a phase comparison signal of No. 2; A comparator circuit and an azimuth adjustment means for adjusting the azimuth W of the reproducing head in a direction in which the phases of the first and second phase comparison signals coincide in response to the high level and low level of the AI inverted signal, respectively. An automatic azimuth adjustment device for a playback head, characterized in that: (2) The azimuth adjustment means is a dead zone setting circuit that monitors the integral information of the inverted signal, and if the value of the integral information is within a preset dead zone, the azimuth al! It was configured in such a way that it didn't have to be lined up! ′
Features Patent R1 Required Range No. 1 (Automatic azimuth adjustment device for a reproducing head as described in item 11). (3) A patent characterized in that the phase comparison circuit includes a D-type flip-flop, and is configured to apply the first and second phase comparison circuit numbers to a data terminal and a clock terminal of the flip-flop. An automatic azimuth adjustment device for a reproducing head according to claims (1) and (2).