JPS5984579A - Schottky junction gate type field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the increase of drain conductance of the titled transistor by a method wherein a stepping of gate depletion form is provided. CONSTITUTION:A source electrode 4 hving ohmic contact and a drain electrode 5 are formed on a semiinsulating GaAs substrate 1 using Au/Ge/Ni and by performing the already-known method. Then, a photoresist 10 is formed on the part which will be turned to a gate electrode, and a dug-in stepping 11 of approximately 300Angstrom is formed at the part located close to the source electrode on the N type GaAs layer 2 of a resist aperture part by performing an ion milling from the diagonal direction of the incidence angle of 30 degrees. Then Ni, as a metal 7 for formation of the Schottky junction of the gate electrode, and Ti 12 and Au 13 are successively vapor-deposited. Then, the photoresist is dissolved using acetone, all metals on the photoresist are removed, and a gate electrode is formed. According to this gate electrode constitution, it has the recess construction or an N<+> structure which is effective for reduction of Rs, and a complete saturation type FET of short gate length having the drain conductance of almost zero on the whole area can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This book relates to a Schottky junction dart-type field effect transistor and a method for manufacturing the same.

(Prior art) Nyotsu I-key coupled gate-carved field effect transistor (hereinafter)
・h' g 'r) at super low frequency and super fast speed.
In the case of υ operation and δ-signal, the gate electrode has a length on the order of rough microns of 1 μm or more. .

The resistance between the source electrode and the gate electrode (i<6
), for example, the recessed structure shown in Fig. 1, or the recessed structure shown in Figs.
Seizo or Ippukuni Tora 71. ing. In the figure, 1 is a semi-insulating GaAS substrate, 2 is an n-type GaA three layer, and 3 is an n+Ga substrate.
As J=, 4 is the source electrode, 5 is the drain 'ljj,
Wa, 7 is Keton Yacht Gi joint formation gold A'B (?Ueha Ni) f 7J<su. Regardless of the structure, the recess or n+ is close to the gate electrode, which is effective in reducing the resistance by 1°C.

Therefore, if the gate length is 4ti'i in the structure shown in Figures 1 to 3, then F E 'I"tl
, θte -voltage 111- in the saturation region of the drain conductor 7 (ga).

The increase in drain contactance gd is FET
When used in 1-4 vessels, etc., it is undesirable as it invites the appearance of Cain's low grapes.

FIG. 4 shows two 11-type GaAs layers with a thickness of about 1,500 cm, with a carrier concentration of K 3 A source electrode 4 and a drain electrode 5, which are sexual contact electrodes, were provided, and in order to form a recessed structure, the n-type GaASφ layer at the extreme part of the gate layer was etched to a depth of 81OOOA, rl]L, 2 μm, and a length of 100 Pm. Perform external 6, Kate length Q, B pm
.

This FET has a gate width of 7n, a gate width of 7n, and an asymmetrical structure as shown in the figure.

Now, Fig. 4 shows the FET characteristics when 101 ohms in total and Rs pole 4 is used as the source electrode, and 5 is used as the drain electrode. VD is the drain voltage.

IDV indicates the drain current.

The sixth element is the ohmic contact electrode 5, the source electrode, and the 4'ff drain electrode in Fig.
qqt property (shown in Figure 7).

As shown in Figure 5 and Figure 7, due to the structure of the gate electrode terminal nayannel, h゛1! L T 11! It can be seen that there is a change in gd (the slope of the current-'voltage characteristic) in the 411 range. 1 In Fig. 4, the gate city pressure (Vg) '+c is constant, and F E 'l''
If the train voltage (VD) increases when the IC is in the 1 range, does the other side of the drain layer 8 of the silicate depletion layer 8 tend to extend toward the drain layer due to the voltage rise distribution? At the junction L in Figure 6, the train direction of the cathode depletion layer -\ is raised! It is 1m shorter and can be easily raised towards the source. Scolding V
(Drain saturation current (IDbs) t and gate depletion 1
9. It depends on the recontactance and electric rise of the notebook. According to the 114th dragon in Figure 4, I am satisfied.
・In the area ↓・I-Is the drain saturation ゛ton Oit 1DssU) increased due to the addition of Jl'i of C1F rain'pressure■D?
It is suppressed by the low conductance due to the extension of the depletion layer toward the drain electrode, and the sixth
In the figure, since the decrease in t Yuconductance is small, ID5S increases, that is, g(1) increases.

Looking at the simple structure of the simple tray above, Figures 4 and 6
In Figure 2, when the thickness a and ao of the portion circled in the figure are close to - or 1, gd becomes small. Here, 0 9 r; J: vibration...'' indicates a depletion layer. Shikaji l〃) is also the 4th
Even in the case of 41 in the figure, the gate voltage (vg) is increased and the voltage rises from the depletion condition to 7t.

(Objective of the Invention) In order to overcome all of the above-mentioned drawbacks, the ``misfire'' was proposed to completely prevent an increase in the drain conductance of a Schottky interlocking type field effect transistor. It is said to be something that has a purpose.

(Creation of the invention) Here, 1. ao project change a. oca demen is Vg
If the condition ≦1 is met, the entire area of the area will be affected by the force. The present invention is realized by providing a step in the shape of the cathode depletion layer as shown in FIG. 8 or 9.

In order to achieve the above-mentioned objective, Kiensu J is Kate's soup 74
The Schottky direction of the electrode is characterized by a shallow step between the drain electrode and the source electrode in the thickness direction of the drain electrode. This is the same as the hidden purpose of the confinement effect.

Furthermore, the "non-explosion" is deep between the Schottky junctions of the gate electrodes or the source "11L" pole side in the thickness direction of the channel, and the drain "tunnel" is shallow with the four-like rule.
The present invention is a Schottky type field-effect transistor in which the electrodes 4'i' and 4'i' + 4'i' and 4'i' have the same characteristics.

δ et al.'tb! JJ It is a Schottky junction with a built-in voltage source A/audience on the source terminal side, and a built-in low voltage metal t-drain electrode connected to it.
1. The purpose of the invention is to create a Schottky-type field-effect transistor with all the characteristics of dirt.

In other words, the present invention is a step of forming a semiconductor layer on a semi-insulating or insulating substrate, and forming a source electrode and a drain electrode on the main surface of the 7ζ wafer to make equal ohmic contact with the semiconductor layer. and a step of forming a photoresist having an entire stripe-shaped opening between the source electrode and the drain electrode, and forming a step or an inclined opening in the photoresist that is deep on the source electrode side on the semiconductor layer and shallow on the drain electrode side. Digging stingray 4Ii, a step of adhering gold Mj k to the entire 1 m of the resist including the opening of the photoresist, dissolving the entire photoresist, and depositing gold kJ4 'fc on the photoresist.
This is the purpose of the invention of the fAA production method for Schottky junction gate field effect transistors, which has all the characteristics of removing process and Kanakura.

The present invention includes a step of completely forming a source electrode and a drain electrode having an ohmic contact with the semiconductor layer on a mound 1 of a wafer in which a semiconductor layer is formed on a semi-insulating substrate or an insulating substrate. , Djj source electrode and drain opening of the striped forest)? Gold kf4 whose Schottky bonding surface does not change during the r-forming process and heat treatment in the 200-400 C1/J temperature range.
K, the front of the photoresist IjijL1 part 1,000 dedicated source 'Ten pole It (II is Mi + written photoresist open') 11111 It is shaded by the wall, A is only on the drain electrode side.
iJ Recording A.''4 The process of diagonally steaming with the direction and angle of impregnation, and heat treatment in the temperature range of 200 to 400 degrees Celsius allows the blood to be transferred to the semiconductor within a year. , 011 Photoresist υi' 41 Conductor 41 of the 41 conductor Asahi of the 11th direction and angle 1ffi strings to nucleate at least the protruding part of the upper beam, and the photoresist bath) +V, and all of the 2 Remove gold J'+i
The process of heat treatment in the temperature range of 200 to 400°C (D) and the process of heat treatment at a temperature range of 200 to 400°C (D) are also included.
It depends on what you are trying to absorb.

1. A semi-insulating substrate, 1. I, 1
On top of the Waeno king with a raw bamboo shape on the substrate, a source electrode and a drain electrode having mechanical contact with the previous layer 2, Ifl, the source electrode and the drain layer are formed. Step of opening IB in the form of stripes in the source electrode and drain electrode holes 111 7.・Resist 7c
In the formation process, the low built-in voltage of the Schottky fitting is caused by the fact that the source electrode side of the half-layer of the potresist layer is shaded by the side wall of the ijU placement resist opening, and the φ of the train's fill is The rays are vaporized obliquely in the direction and angle that makes the gold b) attached, and the hilt-in voltage of the short junction is = iJ 4
= A'J+ 1 opposite metal layer 4 sheath, the above-mentioned photoresist) 1jij step of steaming at least the bh mountain part of the 1 part of the ten binding layer in the direction and angle of the contact, and e) Renst can gamma journey, 1lllN self photoresist.
Two I-steps to remove all metal groups? It is the object of the invention to provide a method for producing a Schottky-conjugated cake-shaped tunic disk having the following characteristics.

Next, an example of VC Kinei Akira's Rinku figure 111+ will be explained. By the way, this is just one example.
lrg god? It is perfectly possible to make individual changes or to save the people as long as it does not cause any unforeseen circumstances.

Example dj to Figure &j', half loquat edge 9 GaAs substrate 1-1
．． FIX p, 1. , 41" I growth Niyori carrier 32.2 X 10">+-' , )"J-3200
OA's n-type GaA31 2 cans epitaxially grown wafer [Using the above n-type GaA3 VC:A--M contact 1'+:L'c source'I-IL4]
and drain '14 yuan (all 5 pots / e /
Ni sheaths can be used in known ways.

(, X vc, 7F in Figure 11,
117.11J, which should be 44 liao, resist thickness 1
．． 2μn7-Jin, 11J1μIn, length 5011m striped paper 1" mouth part 7 pieces 71=) V cyst" 0 product name (AZ-1470) , entering the bed i 7J'' Regime from a 30 degree diagonal direction) 1jr11-1 Miyako's type II GaAs, I
W 2 source 'j, tL4Hjl ('f end bit
'yj', (fJ 3 (by 10A ion ζ-ring A11 included 4・shi: Ker λU\11 and 4 north, 9th book (Kume 715 Ino according to Miring IIc!, 1-mu nakhi channel/channel The thickness is also Nra '3 calendar year Ml I? J70
0Å/7ζ Karuetsu Book 1 Go 9゜Next Kate'i Beni 4
1y('s Schottky'l)
7, Nlt about 200k, disaster 'l'i 12% about 1000^, Au 13k 5000 people fl+7ji7isノ11 °j /) o, Au Qyo ke
- t'iI +x's metal old person (7.(t1t-J:b I-) also o-C2h
9, 'L'l is I'Ji, Au1i? It is 4) Kankako on the I branch of the Kutufa of I. (12th Ward 1 Shun 1
tj) Photo register in the background? , 1・Musuaset〉T ('u
)! j L, Ding'\teno' on the moon midresist, &
hh (!-Remove (Lift Mefuji and Kate electrode sound formation 1.゜Gate width -50μ7N, gate width 10m (Photoresist), opening size), or the gate length for Noah's travel is 'l'' J O, 6pm.
4 mouth 4
'=L, 'ts: /J<L, 1st ξ)
The bad thing is the source rt that was dressed in Figure 13! , QJ< S and train'1.

41. On the other hand, the intermediary is trying to make a plan for you! t1”-
C is bad.

-Jko: Shi 1 Sho 1'' (2) 16th goods 1 to 21 are small party Yu'' other fire〃1tψ1''
Terime.

Figure 16 shows A'C, 1 is a semi-circular GaAs substrate, 2 is A1) IIQ, J < A-YA YJIL 4.1 xio
tjn, type 11 GaAs layer with thickness Y of 120 OA 7. + 6゜n-type GaAs)'isl 2 upper V commerical fitting 7 with source 71a-pole 4 and traino'rlj 4J% 5"rs: ALL/Ge/
Using Nit, 1, water-filled pneumatic cartilage-C 3υ at 450℃
Heat treated for a second to form J Ebisu.

? As shown in Fig. 17, the resist thickness -J is 1.2 μn1 at the bottom position 1i'i, which is the gate pole, and II
J t pm, E+δ50μm (1) Striped opening? Motta photoresist AZ1470 (product name)
10 is formed in a known manner.

7 Missing K J double-crossing the enemy 10 cities of n-type GaA37 meeting f) fJ300 A '+AI', including, recess structure and 1'゜ along with channel thickness noun straightening 9゜ Next 18 (with an angle of 20 degrees in the direction of the drain electrode force) 'r1147f: thickness approximately 600^ diagonally vaporized.

As shown in FIG. 19, 300 ml of Ni 7 was vaporized from the vertical direction.

Heat the photoresist with acetone to remove the gold layer on the photoresist, and form a gate electrode in the shape of J (FIG. 20).

Heat treatment is performed at 300° C. for 10 minutes in an atmosphere of 1-12. Through this heat treatment, Ni 7 becomes n-type GaAs.
Once inside, the Schottky joint surface will sink. (This (-
What is -j technique?L't: l, -ri, for example, Tokugan 1973
4-〇 4642 B, l Also described in ``Manufacturing method of GaAs type barrier gate field effect transistor''1
Melu.

- Sword Ti 14k Schottky gilded part t
The joint surface does not vibrate under the above heat treatment conditions. The joint surface is the lu in Figure 21.
<Step t deep on the source electrode side and shallow on the drain electrode side
It has a firm shape.

In the description of the above embodiments, the heat treatment causes the Schottky joint surface to sink], and the position of the Schottky joint surface to vibrate as Ni? ] l- was used, but in addition to NiQ, Cr, pt, etc. can be used as a phase family in which the position of the Schottky joint surface vibrates by heat treatment at 200° C. to 400° C. In addition, Tik was used as a filler material that does not vibrate on the Schottky joint surface by heat treatment, but in addition to TiQ, 200
U At , W , and Mo can be used as materials whose Schottky joint surface position does not change due to heat treatment at temperatures between .degree. C. and 400.degree.

200℃ was set as the lower limit of the heat treatment condition.
In the case where the bonding m1 is not affected by heat treatment without vortex at 0℃, T
This is because the junction surface is affected by the heat generated by the transistor itself during use, which is not practical. In addition, the upper limit of heat treatment conditions is set at 400℃, and during the transistor manufacturing process, heat treatment at 450℃ is performed to form ohmic contact between the source and drain. Since heat treatment is not preferable, a temperature of 400° C. is used for practical purposes.

FIG. 22 shows the characteristics of the sheet ET manufactured according to the embodiment (2) of the present invention. rl] & 50 μm, apparent length = l pm, effective length = 0,4
It is μm. Figure 23 shows the characteristics when connected to the source electrode and drain electrode shown in Figure 21.

JJ, in fact, there are 4 examples in Figure 20, and the whole story 7 is a commercial money fraud for Hilt-In Electric of Schottky (for example, tyo Pt
), and by making it gold 134147f: a gold stripe with a low built-in pen pressure (for example, 1\40, W),
In particular, in the case of heat treatment J'fL, that is, the Schottky junction plane is on the same half plane; In addition, the drain electrode side becomes shallowly stepped, and the same effect can be obtained.

In addition, FIG. 24 shows that in another modification of the gate electrode structure of the present invention, a deep sloped groove is formed in the gate electrode portion on the source electrode side, and the slope angle r is in line with the gist of ``no failure.'' By configuring the shape of the curved Glue L-depletion layer at a suitable angle, the same effect as in the previous embodiment can be obtained.

Furthermore, in the above description, the shape of the depletion layer is one step, but it may be multi-layered. However, creating an abstract is a complicated process, and there is no particular point as to why.

(Effects of the Invention) As explained above, the gate electrode of the present invention (H structure) has a recessed structure which is effective in reducing R8, or an n+ structure.
It is possible to obtain an 11th type I' ET ?, which has a short gate length and has a drain conductance close to zero over the entire range of the q″f characteristic.

49 Drawing v17rj 4t Celebration 1st to 3rd item 1t The conventional structure FET trouble 1 blood diagram, 4th section 1t The conventional structure ie' E i' operation 1 situation ^F ET 1. lr un diagram, Figure 5 e, F E i' Q characteristic diagram of the structure in Figure 4, Figure 6 is the 1-'
Figure 7 shows an FET characteristic diagram of the structure shown in Figure 6, and Figures 8 and 9 show an example of an FET using the gate electrode structure of the present invention. The ET cross-sectional views and FIGS.
Figure 14 shows the manufacturing process of 'f'.
Figure 15 shows an embodiment of the present invention (P″F '1' 1
16 to 21 are examples of the present invention (
2) % L pole (IJ7 manufacturing process effort i<1FE
T-section W1, Figure 22, and Figure 2 are the fruits of the present invention)
FIG. 24 shows the FE i'il cardiac diagram of Example (2), and the P'ET cross-sectional diagram of the present invention.

■・・・Semi-insulating GaAs substrate, 2・・・・・・
n-type GaAsノ114.3...11 tJa
As layer, 4... Source electrode, 5... Drain electrode, 6... N-type GaA3 j grooved portion, 7... Ketoshosotogi junction forming gold Maple (
Ni), 8... Gutdore 14 criminal] depletion j so, 9... clothing inn q2 layer, IO...
Photoresist, 11... Upsetting of Kate electrode part (ion me link), 12... Foot 'yu,
Extreme gold base ('ll'i), 13...Gate electrode part 4*4 (Au), l<...Kate-Schottky junction forming gold part (Ti).

Patent applicant: Nippon Electric Tsukuda Denzume Corporation Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Vo(V) Figure 6 6 Figure 7 Vo(V) Figure 8 Figure 9 8 Figure 14 Figure 15 Vo(V) Figure 16 Figure 17 Figure 18 Figure 19 Figure 21 14

Claims (1)

[Scope of Claims] (1) The Schottky junction surface of the gate electrode portion is deep on the source electrode side in the floating direction of the nanochannel, and has a shallow step on the drain electrode side. (2) The Schottky junction direction of the gate electrode part is deep on the source electrode side and shallow on the drain electrode side in the J!7 direction of the Nayan channel. A Schottky junction gate type ηL field-effect transistor characterized by a four-layer structure. On the other side of the Schottky junction's Hilt-in voltage sieve source, on the other side, there is a built-in low voltage transistor connected to the Schottky junction on the other side. Gold kJ!' (L Nidrain electrode side + (t) Schottky junction gate type 'Turtle-boosting rice 1 transistor. forming a source electrode and a drain electrode having ohmic contact with the semiconducting layer on the main surface of the wafer having the semiconducting layer formed thereon; and forming a striped opening between the source electrode and the drain electrode. Step 7a--forming a photoresist (section kM); and step of digging deeply at the half-coupled layer gate electrode part of the opening of the photoresist and shallowly at the drain electrode side in a stepped or slanted manner; The Schottky junction gate type is characterized in that it includes a process of applying metal to the entire surface of the resist that has been clamped in the opening, and a process of dissolving the +Y+JH photoresist in a bath and removing the metal on the photoresist the previous day. (5) A source electrode having ohmic contact with the semiconductor layer and a The process of forming the drain electrode sound, forming the photoresist into a shape horn by forming a strife 1 aperture between the source electrode and the drain 4rfx, and forming a 200~400°C tw When heat treatment is carried out in the rx region, the position of the Schottky junction 1 does not change due to the metallic sound, and the photoresist 1 has a half-layered source electrode set 11, which is shaded by the side wall of the opening of the bottom resist and drain. 'f
l、' 4 Scratch the gold maple tray on the glue on the scallop side and the tightening direction and angle l: The process of diagonally steaming with motsu and heat treatment in the 1 hA degree range at 200 to 400 degrees Celsius to make the Schottky contact surface or half cotton. At least Jl of the semiconductor layer of the previous photoresist υi
``Steam the exposed part with the direction and angle of the ridge.
- Be't, (1) Gold JIJ4'? A method for manufacturing a Schottky junction gate field effect transistor, which includes a process of heat treatment at a temperature range of 200 to 400 C and a process of heat treatment in the temperature range of 200 to 400 C. (G'l Semi-insulating 11 board or half-4 on an insulating board)
On the main body 1111 of the wafer which has been cut into a body layer, make ohmic contact with the half body layer.
A process of forming a single drain pole with a drain, and a process of forming a photoresist with a strife-shaped opening k/#Ej between the source and drain widths. , the Schottky junction has a low built-in voltage, and the metal is placed only on the drain electrode side, while the source electrode side of the all-pole r1 front photoresist opening is shaded by the side wall of the photoresist opening. direction and angle t
a step of diagonally depositing the photoresist; a step of depositing the photoresist in a direction and at an angle such that the built-in voltage of the Schottky junction is higher than that of the metal layer; 1. A method for manufacturing a Schottky junction transistor characterized by the removal of all the gold (on the photoresist) and the removal of the rays.