JPS5996584A - Information processing device - Google Patents

Abstract

PURPOSE:To prevent interruption of processing cycle of instruction processed in parallel with block load by writing data in a cash memory in byte width twice as large as byte width in which data are read out from a main memory to a cash writing register. CONSTITUTION:A cash writing register 1071 reads out data having width of N bytes from a main memory 106 when mishit is generated in a cash memory, and writes data of width of 2N bytes in the cash memory 105. Accordingly, data of N-byte width read out from the main memory 106 are stored temporarily in the register 1071 until it becomes data of 2N-byte width. Consequently, temporarily storing time S is raised between timing t6 and t7, and t8 and t9. Accordingly, it becomes possible to process memory read cycle R of instruction 4 which is in parallel with block load cycle M between timing t6 and t7 simultaneously, and processing cycle C4 of instruction 4 is completed at timing t9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus equipped with a cache memory control system.

(Prior Art) A conventional status information processing device of this type has been configured to include a cache memory, a cache memory control circuit, a cache write register, and a write instruction control circuit. The cache memory is provided with copies of a plurality of information block data in the main memory, and exchanges information with the central processing unit instead of the main memory. The cache memory control circuit checks whether the address requested by the central processing unit is registered in the cache memory, and if it is registered, instructs the cache memory to read it, and if it is not registered, a miss is detected. It sends a block load request to the main memory as follows. The cache write register buffers N (positive integer) byte 1-width data read from the above-mentioned Chapter 44 device when performing a block load, and writes it into the cache memory. The write instruction control circuit receives a write instruction from the cache memory control circuit and instructs the cache memory to write data from the cache adjustment register into the cache memory.

Next, a conventional example will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional information processing apparatus, and FIG. 2 is a timing diagram illustrating an example of the operation of the conventional example shown in FIG. tflW1. Central processing unit 1011-
j: Cache memory control circuit 103 via signal line 1
is activated at any time and executes a series of instructions while accessing the cache memory 105.

In the instruction execution process, the execution of the instruction and the preparation of data and instructions are performed in parallel, which speeds up the execution of the instruction as a whole. Ranarai. Prefetching of an instruction is performed when the cache memory 105 is not accessed from the central processing word +R101 via the signal line 1. First, the instruction prefetch circuit 102 activates the cache memory control circuit 103 via the signal line 2, accesses the cache memory 105, and reads data ili! from the cache memory 105. i! 1
1, the command is read out via the first data switching circuit 10B. Next, a buffer link [2
This is done by keeping it. The instructions buffered in the instruction buffer 121 are sent to the central processing unit 12 as shown in the processing cycle C2 of instruction 2 shown in FIG.
1, and is processed in the following order: instruction decode cycle D, address decrement cycle A, memory read cycle R2 execution cycle E, and storage cycle W for writing the execution result into memory. Conventionally, most of the large-scale A computers that perform high-speed processing are the above-mentioned A and R.

It is equipped with processing units corresponding to each cycle of E and W, and constitutes one central processing unit as a whole.

Commands and data are processed by passing through each processing cycle once, but these commands and data flow through each processing device without interruption. 91',' In FIG. 2, as shown by the processing cycle C2 of instruction 2 and the processing cycle C3 of instruction 3, each process proceeds in parallel. This kind of place, the burial type, is called a pie brine.

Although the above explanation has been made on the assumption that the memory address requested by the central processing unit 101 is always registered in the cache memory 105, so-called misses may occur.

The central processing unit 101 has a cache memory control circuit 103
The cache memory control circuit 103 first checks whether the requested memory address is registered in the cache memory 105 at tIi. If it is registered, it will be processed according to the procedure described above, but if it is not registered, a mishit will occur. Therefore, the cache memory control circuit 103 sends an instruction to execute a block load to the frosting instruction control circuit 104 through the input line 5, and at the same time accesses the if(device 106) via the signal line 6. 1 for multiple pages
These pages (c) are further divided into blocks, each consisting of multiple words. Main storage device 10
In step 6, a block load cycle is executed for e- in order to increase the subsequent hit rate. That is, the central processing unit 101
One block size worth of memory address data starting from the requested memory address is stored in the cache, and N bytes are stored in one block inside the cache memory 105 via the data signal lines 9 and 10 while being buffered by the register 107. Enter ■ with 11Qg. At this time, the read data switching circuit 108) receives an instruction from the cache memory control circuit 103 via the data signal line 4, and connects the data signal line 10 and the signal line 12. Therefore, in parallel with block loading, data from the cache write register 107 is directly transferred to the central processing unit 10.
1, and the operation of retrieving necessary data from the cache memory 105 after block loading can be omitted. Here, the signal line 1 is a signal line for a read signal of the cache memory 105, and the signal line 1 is a signal line for a write signal of the cache memory 105.
Signal line 8 is a signal line for a write signal of cash draw register 107.

In FIG. 2, a miss occurs to the memory address determined by the address subtraction cycle ~A between timings t2 and L3, and after a wait time of turnaround time Y due to the block load cycle M, the main Data is written from the storage device 106 to the cache write register 107.

The write operation is performed at S between timings t5 and t6.
K is represented. Data written to cache write register 107 between timings t6 and t6 is written to cache memory 105 in the morning between timings t6 and t7.

To express this, at the same time, the following data is loaded from the main memory 106 to the register 107 in the cache 114. In this case, timing t6
Cache memory 1 between 101 and timing tin
Since the write operation to 05 is performed, the central processing unit 10
1 cannot access the cache memory 105. Therefore, among the processing cycles of instructions following the processing cycle C1 of instruction 1, the memory read cycle R of instruction 4 that is parallel to the block load cycle M is at timing t6.
The process ends at timing t13 of the instruction 4 processing cycle C41.

As explained above, in such a conventional configuration, when a U miss occurs, the cache memory is constrained during the block load cycle, making it impossible for the central processing unit to access it, and the instruction The disadvantage is that the processing time is long.

(Objective of the Invention) The object of the present invention is to write data to the cache memory in a byte width twice the byte width read from the main storage device to the cache storage register, so that when a miss occurs, Another object of the present invention is to provide an information processing device in which a cache memory is bound to a cache write register to free up idle time, thereby preventing interruption of the processing cycle of instructions being processed in parallel with block loading. be.

(Structure of the Invention) According to the present invention, 1) the information processing device includes a cache memory;
This system is composed of a cache memory control circuit, a cache write register, and a write instruction control circuit, but the internal configuration is different from the conventional system.
That is, the cache memory is equipped with multiple information block loads lf:, l of the prison storage device f6, and exchanges information with the central processing unit 1'7 instead of the λ-2 main storage device. . Is the cache memory control circuit a central processing unit? Check whether the requested address is registered in the cache memory or not. The cache write register has a capacity M° of 2N bytes, which temporarily stores a data word of N (tF integer) bytes wide read from the main memory when a block is loaded, and writes it to the cache memory when necessary. It is. 71 included instruction control circuit is cache memory ftjl! ff1ll k'
When the data word read from the main memory to the cache draw register upon receiving a write instruction from the Il path is a random line, the contents of the next address are also read to the cache write register, and 2N byte wide data is selected. Sends a write instruction to the cache memory at one point, and if it is an odd number, the data is sent to the cache memory without waiting for the next data)
This command gives an instruction to the cache 11 register and the cache memory to load the cache 11.

(Example) Next, regarding the 2j17@ example of the present invention, 1.
Is 4shi the liver? Explain the purpose.

Meeting r1, 3 figure i+: * '6 & light, t: le ('F
f? 13#LFIV,e fi'j 〕-''+tfu+t
Fij: block times = F), rabbit 4 figure 1 ', 3
1'+'l &il'T11 of Isong 7ii1i example shown here
It is a timing diagram for changing the angle to 4J, i.

Furthermore, 5th goods 1t1, Inu Yash 71 included register.

Concern 1) Included instruction flt control circuit and cashmeco f-
11 is a circuit diagram showing an example of the part of the
'I, Figure 6 and Figure 7 are t-1. That is, the sixth
When the block load start address of FIG. 7 is the address of Tsukuda V, FIG.

If a miss occurs in the memory of the cache register 1071 shown in FIG. KI “
Then, data with a width of 2N bytes is loaded into the cache memory 105. Therefore, main memory 106
Read from the cache write register 1071 (~N byte wide data becomes 2N byte 1 data)
111 Jr. is remembered inside. For this reason, as shown in FIG.
Between 6 and t7, O, 1: and timing L8 and L
9 [J3 can now be issued, and in this period ■η 1 cache memory 105 (r ↓ is not bound to the cache evening register 1071, therefore, block row 1
Memory read cycle I of instruction 4 parallel to cycle M
(, block low 1 between timing ts and ty)
Since it is now possible to process cycle M in parallel, processing cycle C4It:f of instruction 4 ends at 9 on timing. According to the prior art, as shown in FIG. 2, the processing cycle C4 of instruction 4 ends at timing t13, so the processing cycle C4 of instruction 4 is shortened by 4 timings. It turns out. Here, the data signal lines 10a, 10b (rl: each is for transferring a data signal of N byte width, and one of the data signal lines 10a, 10b, 11 is selected by the read data switching circuit 1081. Ru.

Here, it is a switching signal of the signal line 4a output switching circuit 1081.

Next, FIG. 5, FIG. 6, and FIG. 7 will be explained in detail. Data register 9a caches data from main memory 106 to write register 10711.

10712. The signal on signal line 13 is generated by cache memory control circuit 103 and serves as a data entry signal for cache write registers 10711, 10712 and cache memory 105. Signal line 19
The upper signal is an address signal generated by the cache memory control circuit 103, and the address switching circuit 10
9 is set in the address register 110. In addition, the address count up circuit 11 is applied to the address signal.
It is incremented by 1. The signal on signal line 27 is a switching signal of address switching circuit 109 and is generated by cache memory control circuit 103 . The signal d address on the signal line 20 (□ is the least significant bit signal of the open circuit 109, and the address register 1 is connected to the number A of the signal line 23-J:
10 output signals. These are the remaining bit signals excluding the h3F bit of the signal address register 110 on the signal line 21. Is the signal on Iba No. 128°30 a cache memory? Data retrieval M'('``I'' of the cache memory 105 generated by the li control circuit 103
(M Rtef'>6゜(r'i ”i i!i!
The signal on 16 is generated by the memory control 1 circuit 103 and is a signal for generating a data write timing pulse for the memory 105.

In Figure 6, the block load start address is (fi!+K
This is an operation timing diagram for the case of the A address, and a timing diagram corresponding to the operation of each signal line of the fifth (S). FIG. 7 is a similar timing diagram for the case where the block load start address is an odd E'JM address. It is a diagram.

The operation of FIG. 5 will be explained below while referring to FIGS. 6 and 7. When loading a block, the main memory 10
Data is transferred from 6 through data line 9a, and a block load start address is sent out through signal line 19 through 7. In this embodiment, the signal line 27 selects the A line 19 at this time.

In FIGS. 6 and 7, the state of the signal line 27 is % 1
When the state is N, the signal line 19 is selected, and when the state of the signal line 27 is %01, the signal line 24 is selected.

If the block load start address is an even address, the state of the signal on the signal line 20 becomes 0, and the data is written on the signal line 13 and the inverter outputs from the third gate 133 on the signal line 25. The second gate 13
2, the ANI) Φ condition is established, the state 11 of No. 44 on the data 111 input signal line 14 of the cache write register 10711 becomes -11, and the memory data is stored.

(?+'t' 1 at 61ya, the timing between The state of the signal becomes -1, and the 2T delay circuit 112 is activated. (Refer to the timing between t2 and t3 in Figures f, 11 and 6.) In this embodiment, when the block load start address is an even number address (
E? The states of the signals on the line 2B30 are both IN. (See the timing between t2 and tll in FIG. 6.) The output of the 2T delay circuit 112 is sent out via the signal line 18, and since the state is O at the current timing, the fifth ANDφ of gates 135 and 136 of flood 6
condition is not established, and the status i? The power is 0, and the contents of the cache "f1 register 1071 are not written to the cache memory 105. (Mo2 and t3 in FIG.
At the next timing, the address switching circuit 10a selects the signal line 24 so that the signal line 2γ selects the signal line 24. I will control you. (t3 in Figure 6
See the timing between and t4. ) A block load start address is set in the address register 110 via the associated address signal line 22. Itami #20-1:
1, the state of No. 1 IJ44 becomes 1 f, and from this signal and the positive output of 14J13 game l-133, the signal line 26
An AND condition is established by the first gate 131 with a signal sent out via
1 #, and the memory data is (nominated).As a result, the cash store 4-inclusive register 10711.10
Data is stored in 712.

Furthermore, at the next timing, the address count up circuit 111 starts the block load.
Address No. 18, whose address is incremented by 1, becomes 0 again, and new data 71 is pulled into the Gash W↑-include register 10711 at the above and times 41if. Also, at this timing, the state of the 21 delay i4 circuit 11201h is -17, and the state of the signal on the signal line 28.30 is 1 as described above. Therefore, the AND condition is established by the fifth and sixth gates 135 and 136, and the data write signal line 29.
The state of the signal on 31 becomes 11. Therefore, at the same time new data is written to cache write register IQ711, cache write register 1
The data written in 0711 is stored in cache memory 1 along with the contents of cache write register 10712.
Written to 05. Block loading is executed by repeating the above IJ operation. When the block load is completed, the address switching circuit 109 is controlled by the signal line 27 so that the signal line 19 is selected, and the
The state of the signal above 28°30 will be %0#. (See the timing between tlo and tll in Figure 6.) Next, consider the case where the block load start address is address t9 on the right. When the block load starts, the signal on signal line 20 is In state 9, the number is dormitory 1, and data is first written to the cache 6fL register 10712. (Refer to the timing between L2 and t3 in FIG. 7.) At the next timing, the address is counted up, the state of No. 48 on the signal net 2o becomes 0, and the data is stored in the cash store register 10711. It's blue. (See the timing between t3 and t,4 in FIG. 7.) Furthermore, only the data in the cache write register 10712 is pulled into the cache memory 105 at this timing. Therefore, at the current timing, 2
The state of the signal on the signal line 16 is set to -II before IT (timing) when the cache memory control circuit 103 starts block loading so that the state of the output of the delay circuit 112 becomes -II. (See the timing between 11 and t2 in Figure 7)! ! In addition, the cache memory control circuit 103 changes the state of the signal on the signal line 2B to 11g so that only the data in the cache write register 10712 is written into the cache memory 105 according to the current timing.
/L, and also change the state of the signal on the signal line 30 to 11.
to 〃. (See the timing between t3 and t4 in FIG. 7.) With this control, the AND condition is satisfied only by the sixth gate 136 among the fifth and sixth gates 135 and 136. write register 1
The data of 0712 is written into the data storage memory 105.

At the next timing, the state of the signal on the signal line 20 is % 1
1, new data is pulled into the cache write register 10712. (See the timing between E4 and t5 in FIG. 7.) Furthermore, at the next timing, the state of the signal on the signal line 20 becomes 0, and new data will be drawn into the cash draw register 10711. shall be.

(See the timing between t5 and t6 in FIG. 7.) At this time, the output state 8 of the 2T delay circuit 112 becomes 1, but the signal i! Since the states of the signals on 1128.30 are both controlled to % IN, AN, D! The condition is satisfied, and new data is written into the cache write register 10711. At the same time, data d, which had been previously stored in the cash register 10711, is stored in the cache memory 115 along with the contents of the cache write register 10712. The block load continues in this manner, but when the data is finally written to the cache pull register 10711, the block load ends. (to and tl in Figure 7.

See timing between. ) This data is written to the cache memory 105 at a timing between tll and tl2 in FIG. At this time, only the contents of the cache write register 10711 are stored in the cache memory 10.
5, the state of the signal f14 on the signal line 28 is changed to L'l 1 // by the insertion instruction control circuit 1141, and the state of the irises 3) on the signal line 30 is changed to 0. Ru.

In this embodiment, the first load is executed as described above, but the key number F29,31+ and the number 1 of the memory backloading is 6th in FIG.
;Imming t2-t4 +j! l to +j7
"[1+'9- jl.

In FIG. During this time, the central processing unit 101 can access the cache memory 105.

(Effects of the Invention) As explained above, the present invention has a byte that is read from the main memory instead of pulling data into the cache memory in the same byte width as the MP and output from the main memory by the cache write register. By configuring the data to be written in a byte width twice the width, even when a miss occurs, free time is created where the cache memory is not tied to the cache pull register, and the block load Since it is possible to prevent interruption of the processing cycle of instructions being processed in parallel, this has the effect of significantly shortening the instruction processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram 1 showing an example of a conventional information processing device 17. As shown in FIG. Figure 2 &'iage 1, Figure 1 shows 41 - Information processing device K1
FIG. 2 is a timing chart showing the operation of FIG. FIG. 3 is a block diagram 1 showing an embodiment of the information processing apparatus according to the present invention. FIG. 4 is a timing diagram showing the operation of the information processing apparatus shown in FIG. FIG. 5 is a block diagram showing details of the cache write register, write instruction control circuit, and cache memory in the information processing apparatus of FIG. 3 according to the present invention. Figures 6 and 7 show the details of the operation timing of the circuit part in Figure 5. Figure 6 shows the case where the block load start address is an even address, and Figure 7 shows the case where the block load start address is an even address. FIG. 7 is a diagram illustrating operation timings in the case of odd addresses. 101...Central processing unit 102...Instruction prefetch circuit 103-@cache memory control circuit 104.104
1... Penetration instruction control circuit 105... Cache memory 106... Main storage device 107, 1071, 10711, 10712... See-
Cache write register ioa, ioa1...read data l; II conversion circuit 1
09.--Address switching circuit 110.9.Address register 111.Fist e address count up circuit 112..Φ
2T delay circuit 121・instruction buffer C1~C4・
911 instruction processing cycle M, J), A, R, E, W, Y
, S, L -----...Processing details
31, 4a, 9a, 10a, 10b*e*...Signal #
;1 Patent Applicant NEC Co., Ltd. Agent Patent Attorney

Claims (1)

[Scope of Claims] A cache memory that is provided with copies of a plurality of information block data in a main memory and that exchanges information with a central processing unit instead of the main memory. It is checked whether the address requested by the central processing unit is registered in the cache memory or not, and if it is registered, a read instruction is sent to the cache memory (111), and if it is not registered, a miss is detected. a cache memory tltll 111 circuit for sending a block load request to the main storage device, and a cache memory tltll 111 circuit for sending a block load request to the main storage device, and an N (positive integer) byte width A separate cache register with a capacity of 2N bytes for temporarily storing data words and loading them into the cache memory when necessary, and receiving loading instructions from the previous HO cache memory control circuit. When the address of the data word read from the prison storage device ffJ to the cache write register is an even address, the contents of the address next to C1 are also read and output to the cache write register, and the 2N byte wide data is 'tii1. At this point, the cache write register and the cache memory are instructed to write to the cache memory, and when the address is an odd address, the data is written to the cache memory without waiting for the next data. write instruction IN for instructing the cache write register and the cache memory register;
An information processing device consisting of +Go1i'ilro and Ken2.