JPS60102762A - 集積回路基板の電極製造方法 - Google Patents

集積回路基板の電極製造方法

Info

Publication number
JPS60102762A
JPS60102762A JP58209072A JP20907283A JPS60102762A JP S60102762 A JPS60102762 A JP S60102762A JP 58209072 A JP58209072 A JP 58209072A JP 20907283 A JP20907283 A JP 20907283A JP S60102762 A JPS60102762 A JP S60102762A
Authority
JP
Japan
Prior art keywords
photoresist
layer
electrode
shape
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58209072A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0443417B2 (2
Inventor
Akira Murata
旻 村田
Muneo Oshima
大島 宗夫
Masaru Sakaguchi
勝 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58209072A priority Critical patent/JPS60102762A/ja
Publication of JPS60102762A publication Critical patent/JPS60102762A/ja
Publication of JPH0443417B2 publication Critical patent/JPH0443417B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041Photolithographic processes

Landscapes

  • Wire Bonding (AREA)
JP58209072A 1983-11-09 1983-11-09 集積回路基板の電極製造方法 Granted JPS60102762A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58209072A JPS60102762A (ja) 1983-11-09 1983-11-09 集積回路基板の電極製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58209072A JPS60102762A (ja) 1983-11-09 1983-11-09 集積回路基板の電極製造方法

Publications (2)

Publication Number Publication Date
JPS60102762A true JPS60102762A (ja) 1985-06-06
JPH0443417B2 JPH0443417B2 (2) 1992-07-16

Family

ID=16566785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58209072A Granted JPS60102762A (ja) 1983-11-09 1983-11-09 集積回路基板の電極製造方法

Country Status (1)

Country Link
JP (1) JPS60102762A (2)

Also Published As

Publication number Publication date
JPH0443417B2 (2) 1992-07-16

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