JPS60107856A - Manufacture of cmosic (complementary metal oxide semiconductor integrated circuit) - Google Patents

Abstract

PURPOSE:To simplify the matching of threshold voltage by a method wherein, after a gate electrode consisting of a gate oxide film and a polycrystalline Si has been formed, impurity ions are implanted into the source and drain region on one MOSFET, which is a conductive type region, and the channel stopper region of the other MOSFET, and said impurity ions are diffused by performing a heat treatment. CONSTITUTION:A P type well region 3 is formed by diffusion on the surface layer part of an N type Si substrate 1, a gate oxide film 10 and a polycrystalline Si layer 11 are coated on the entire surface, a photo-etching is performed on the layer 11, and gate electrodes 11a and 11b consisting of a layer 11 are formed on the region 3 and the other region respectively. Then, a resist mask 61 is coated on the channel stopper region of N-channel MOSFET and the region other than the part which will be turned to the source and drain region of a P- channel MOSFET, and a P type ion implantation layer 5 is formed. Subsequently, the mask 61 is replaced by a mask 62, an N type ion implantation layer 7 is provided, and two FET stopper regions 51 and 71 and source and drain regions 52 and 72 are formed simultaneously by performing a heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention involves diffusion for forming the source and drain regions of a N-channel MO8FET and a P-channel MO8FET on a single silicon plate using gate electrodes as masks. The present invention relates to a method of manufacturing CMOS IO using a self-alignment method.

[Prior art and its problems]

There are two methods for manufacturing OMo 8 IO: the AI agate method, in which a gate oxide film is formed after forming the source and drain regions of N-channel and P-channel MO8FETs, and an Al gate electrode is formed thereon; A self-aligned method is known in which after forming a gate electrode using a melting point metal, diffusion is performed using the gate electrode as a mask to form the source and drain regions of N-channel and P-channel MO8FETs, but the channel length increases with miniaturization. From the viewpoint of strict control of gate electrode formation, self-alignment methods that do not require mask alignment for gate electrode formation have been widely used. By the way, in this latter method, the process is performed prior to the gate oxide film formation process or the N-channel and P-channel source/drain diffusion processes, which have a large effect on determining the dark voltage, so care must be taken to control the threshold voltage. need to pay. Figure 1 (f) ~ 0 is Si Age-CMO using self-alignment method
As shown in FIG. 1, P-type impurities are diffused into a part of the main surface of an N-type silicon substrate 1 using an oxide film 2 as a mask to form a P-well region 3.

After that, as shown in FIG. 1 (+3), 0), resist 4
After performing impurity ion implantation 5 for forming a channel stopper for N-channel MO8FIuT using as a mask, impurity ion implantation 7 for forming a channel stopper for P-channel MO8FET using resist 6 as a mask, as shown in FIG. By selectively oxidizing the nitride film 8 using the nitride film 8 as a mask, a thick 1-oxide film 9 is formed in the field portion, and at the same time, a channel stopper diffusion layer 51.71 is formed. Next, a gate oxide film 10 and a polycrystalline silicon layer 11 are formed and processed into a gate electrode structure as shown in FIG.

The layer 12 is plugged, and the source and drain diffusion layers 13 of the N-channel MO8FET are formed using the polysilicon 11 as a mask. Next, as shown in FIG. 1, the active region on the N-channel MO8FBT side is
Then, using the polycrystalline silicon layer 11 as a mask, source and drain diffusion layers 15 of a P-channel MO8FET are formed. After that, the entire surface is covered with a surface protective film 16.
), N-channel and P-channel MO8FET sources, gates.

A drain contact hole is formed and an Al electrode 17 is provided (FIG. 1, t(l). As described above, in the conventional method, the P-type region 3 is formed and the channel stopper 51.7 is formed.
1 and field dielectric film 9 formed, gate oxide film 10 formed, source and drain regions 1 of N-channel MO8FET
There are heat treatment steps such as formation of source and drain regions 15 of the P-channel MO5-FET, and the wafer undergoes thermal history many times. This increases the risk of generating crystal defects such as at the silicon-oxide film interface. Especially after forming the gate oxide film, N-channel and P-channel M
Sequentially performing source and drain diffusion of O81T
There are significant problems in matching the threshold voltages of N-channel and P-channel MO8FETs.

That is, the interface between silicon and the gate oxide film on the N-channel MO8FET side is subjected to one more heat treatment than on the P-channel MO8FET side, which causes a difference in the generation of interface states.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, enables arbitrary and easy matching of threshold voltages of P-channel and N-channel MO8FETs, and manufactures a self-aligned OMOS IO with a simpler process. The purpose is to provide a method.

[Key points of the invention]

The method for manufacturing an OMOS IO according to the present invention includes: - a step of forming one well region by diffusion of impurities in a part of the main surface of a conductive type silicon substrate; and a step of covering the same main surface of the silicon substrate with an oxide film. and a step of forming a polycrystalline silicon layer that will become each gate electrode on the region of the oxide film that will become each gate oxide film at a low temperature that does not affect the interface level of the gate oxide film, and one MOSFET. source.

A step of implanting P-type impurities or N-type impurities for the drain region and the channel stopper region of the other MOSFET into the portions of the main surface that will become these regions, respectively, using a camphor film as a mask, and after removing the insulating film, the gate A surface protective film can be easily deposited on the entire surface at a low temperature that does not affect the interface states under the oxide film with good yield.

[Embodiment of the Invention] - Fig. 2 Q to D show manufacturing steps of an embodiment of the present invention, and parts common to Fig. 1 are given the same reference numerals. There is no difference from the case in FIG. 1 up to the formation of the P-well. That is, as shown in FIG. 2(f), P-type impurities are diffused into a part of the main surface of N-type silicon substrate 1 using oxide film 2 as a mask to form P-well region 3. Next, the oxide film 2 is completely removed, and a gate oxide film 10 and a polycrystalline silicon layer 11 are formed over the entire surface (FIG. 2B). Thereafter, polycrystalline silicon layer 11 is processed by photoetching to form gate electrodes 11a and llb, and N-channel MO8
FET channel stopper region and P channel MO8
The regions other than those to become the source and drain regions of the FET are masked with a resist 61, and a P-type impurity implantation layer 5 is formed by ion implantation (FIG. 20). Next, after removing the resist 61, as shown in FIG. 2O, a channel stopper region of a P-channel MO8FET and a source, gate, and drain region of an N-channel are newly formed. The regions other than the desired portions are masked with a resist 62, and an N-type impurity implantation layer 7 is formed by ion implantation. In this case, the polysilicon layer 11a is doped with N-type impurities, and the polysilicon layer 11b is doped with P-type impurities.
However, if the thickness of the polysilicon layer 11 is appropriately selected, the gate oxide film 10 under the polysilicon layer can be implanted.
It will not cause any damage. Next, the resist 62 is removed and a low-temperature 0VDSiO, 14 is formed on the entire surface, and this is used as a field oxide film. Thereafter, by annealing under appropriate heat treatment conditions, channel stopper regions 51.71 and source and drain regions 72.52 of N-channel and P-channel MOSFETs are formed at once. This heat treatment is performed at a low temperature of 0VDS40. It also serves as annealing for the film 14 (Fig. 2@). Next, N cha is formed (second
Figure D). In the above manufacturing method, the impurity concentration of the substrate is reduced to 1
011~101'cIIL', P well impurity concentration 1.45X10"cm'4, gate oxide film thickness 0.08
μm1 polysilicon layer thickness 0.5 μm, P channel, Ru and N channel sources by ion implantation.

If the impurity dose of the drain region is 2×10”♂, the thickness of the 0VDSi02 field oxide film is 0.5 μm, and heat treatment is performed at about 1000° C., an N-channel can be formed.

Dark value voltage IVthl=0 for both P-channel MO8FETs.
6■ is obtained. By the way, the field MO in this case is
The threshold voltage of the 8-FET was 60V or higher. According to the method described above, by arbitrarily selecting the substrate concentration, oxide film thickness, P-fer concentration, ion implantation dose, and heat treatment temperature, the N-channel MO8FFiT and P-channel MO8FET can be adjusted for any threshold voltage. It is possible to achieve consistency.

〔Effect of the invention〕

In the present invention, after forming a gate electrode consisting of a gate oxide film and a polycrystalline silicon layer, one MOS becomes a region of the same conductivity type.
FET source and drain regions and the other (1') MOSF
After implanting impurities for the channel stopper region of the ET, the source, drain and channel stopper regions of both MO8FETs are simultaneously diffused. High temperature heat treatment after oxide film formation (400
℃ or higher) only once, which reduces problems such as property fluctuations, wafer warping, and crystal defects caused by thermal history, and improves the yield of 0M08IOg fabrication and simplifies the process. is extremely thick.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view sequentially showing the manufacturing process of a conventional OMOS IO, and FIG. 2 is a cross-sectional view sequentially showing the manufacturing process of an embodiment of the present invention. 1... N type silicon substrate, 3... P well region, 5
...P type impurity ion implantation, 7...N type impurity ion implantation, lO...gate oxide film, 11...polycrystalline silicon layer, lla, llb...gate electrode, 51.7
1... Channel stopper region, 52.72... Source. Drain region, 61.62...resist.

Claims (1)

[Claims] 1)-A step of forming one well region of another conductivity type on a part of the main surface of a conductivity type silicon substrate by diffusion of impurities, a step of covering the main surface of the silicon substrate with an oxide film, and a step of nucleic oxidation. forming a polycrystalline silicon layer that will become each gate electrode on a region of the film that will become each gate oxide film at a low temperature that does not affect the interface level of the gate oxide film;
A step of implanting P-type or N-type impurities for the source and drain regions of one MOSFET and the channel stopper region of the other MOSFET into the portions of the main surface that will become these regions, using an insulating film as a mask, After removing the film, a step of depositing a surface protection film on the entire surface at a low temperature that does not affect the interface states under the gate oxide film, and a step of heat treatment for driving the implanted impurities are sequentially performed. A manufacturing method of OMOS IO characterized by: