JPS60132253A - Address converting system - Google Patents

Abstract

PURPOSE:To execute simultaneously the address conversion of plural continuous pages by a small quantity of hardware by executing the address conversion by taking notice that it extends over several pages continued in the same direction in vector operation. CONSTITUTION:In case of a vector operation, an object data of the same operation often extends over plural pages, therefore, a processing device sets the head logical address signal of an element to be brought to an access at a stroke, to an address register 1, and also sets direction information to a direction information register 2. The direction information designates a page to be brought to an address conversion together with a page designated by the first page number P1 and the second page number P2. Operators 3, 4 execute an operation of +1 and -1 to a value of the first page number P by + and - of the direction information, and its result is selected by a switching device 6 in accordance with a switching signal which an address adjusting circuit 5 sends out basing on the direction information and a value of the second page number P2, supplied to converting buffers 10-13, and read out by registers 14-17.

Description

DETAILED DESCRIPTION OF THE INVENTION In the present invention, so-called vector calculations are mainly performed, in which the same calculations are performed in address conversion power suitable for vector calculations, image processing in the field of search for sources, and the like.

Each element in the array is stored in a relatively slow main memory, and is stored in the array element's first address of 0 and the inter-element distance of 0 in the row, column, diagonal, etc. ( B+
1D) (i is an integer) read out to the processing device at regular intervals,
After arithmetic processing, it is stored at the same or different address. Since the array data handled is generally larger than the capacity of the main memory, the so-called virtual memory method converts logical addresses on the program to real addresses based on an address conversion table and accesses the main memory. It is common to take .

In order to perform address translation at high speed, many devices are equipped with an address translation buffer 7 (hereinafter abbreviated as translation buffer) to hold a copy of the address translation table stored in the main memory. In order to improve the performance of a processing device that performs vector operations, it is important to have access to the main memory that is commensurate with the internal processing speed.

This type of conventional address translation method provides a plurality of translation buffers, reads address translation data for multiple pages at the same time, and processes main memory accesses for multiple pages at the same time.

The aim is to improve data throughput with the main storage device.

In such a conventional configuration, since a plurality of conversion buffers are provided, there is a drawback that the amount of hardware is increased.

Other conventional address translation methods of this type include one that divides the translation buffer and interleaves all accesses to achieve an effect similar to that described above with a small amount of hardware.

However, with this conventional configuration, we focused on the drawback that only one address translation can be performed at the same time and that it often spans several consecutive pages in the same direction. The logical address space is equally divided into pages by the upper M bits of the logical address signal and the N bits following the M bits, and each page is divided into two M bits for the page, each having the same contents of the N bits. 2 to N conversion buffers that store part or all of several pieces of address conversion data; at least one arithmetic unit that adds or subtracts 1 to the contents of the M bits; and at least the N bits. an address adjustment circuit that generates a switching signal corresponding to the conversion buffer based on the contents of the conversion buffer; FIG. 1 shows an embodiment of the present invention in which a switch and a metal switch corresponding to the conversion buffer 1 as a signal are provided, and real page addresses for consecutive 2ON multiplier pages from the page designated by the logical address signal are obtained at once. FIG. 2 is a block diagram showing one embodiment.

In this embodiment, address registers 1 and 14 of 5 ItIj
15.16 and 17, direction information register 2, adder 3, subtracter 4, address adjustment circuit 5, four switches 6, 7, 8 and 9, and four conversion buffers 10
, 11, 12 and 13.

A 28-bit logical address signal can be set in the address register 1 by a processing device (not shown) so that two logical addresses that can be specified by a program can be specified. The upper 6 pits, 2 bits, and 20 pits of the logical address signal are respectively the upper page banding P8, the lower page number P, and the intra-page address A.
It is for expressing i. In other words, the logical address space consists of 256 pages (one page is 22°'±1.0
48,576 addresses).

A page is specified by an upper page number P and a lower page number P, and each of the conversion buffers 10, 11, 12, and 13 converts the addresses of the 21 upper page numbers for pages having the same lower page number P2. Store data. That is, the conversion buffers 10, 11, 12, and 13 have lower page numbers P2 of O, 1, and 2, respectively.
This corresponds to a page group (consisting of 64 pages) of and.

FIG. 2 shows the relationship between logical addresses and real addresses in this embodiment. The logical page ΔP expressed by the first page number P and the second page number P2 is the real page RP (
This real page RP and intra-page address A (same as the logical address) are used to directly access the main memory (not shown). By loading pages into main memory, the program can handle the data as if there were 256 pages, eight times as many.

Address conversion data for performing the above address conversion is stored in the main storage device along with programs and other data. From this address translation data,
Conversion bags 710 to 13 each consisting of 64 address conversion data for 64 pages in cylinder speed memory
address translation table is preloaded from main memory.

Now, the processing device executes the above 1. according to the program. reads the instruction in the device, solves the instruction φl, calculates the mevesindo address, reads the operand data stored directly in the main memory if necessary, and performs the promotion process.
A series of data processing is performed in which the calculation results are stored in the main memory if necessary. In the process of processing these data, address conversion as described above is performed every time an access to the main memory is required.

In the case of vector operations, the target data for the same operation often spans several pages of values, so the processing unit directly sets the first logical address signal of the element to be accessed every time in address register 1, and also sets the direction Set direction information in information register 2. The direction information is the first page number P of the logical address signals set in the address register 1.
1 and the second page number P, is used to specify the page on which address translation is to be performed.

Figures 3 and 11g1 to 3.8 are diagrams to make this easier to understand. Figure 3.8 corresponds to the case where the direction information is negative. Each of the numbers 0, i, 2, and 3 in FIGS. 3, 1 to 3, and 8 is the value of the second page number P.
, 11, 12, and 13 specify the address conversion table stored therein. Also symbols X-1, X and X+
1 indicates the value of the first page number P1.

Number 0, 1.2 or 3 and symbol X-1, X or X+1
The block designated by and indicates the real page for a specific page in each address conversion table, and the symbol
The first page number P1 and the second page number P set to
The values of are shown respectively.

In Figure 3.1, if a page whose second page number P is 0 is set in the address register 1, and plus is set in the direction information register 2 as the direction +'f4 information, then the symbol
Translation buffers 10111.12 and 13 accessed by x(o), respectively.

X(1), X(2), and X(3)) indicates that the husband page is read out. In Figures 3 and 2, the page whose second page number P is 1 is the address register l.
, and 5 plus is set in the direction information register 2 as the direction information. In this case, X(1),
Real pages are being extracted from X(2), X(3) and X-)-1(0). This indicates that the fourth real page is read from address X+1 of translation buffer yl-0. The intent of FIGS. 3.3 and 364 can be easily understood by using a similar concept.

Each of Figures 3.5 to 3 and 8 shows the case where rL in Figures 3.1 to 3 and 4 is given the glass direction 4W information, while the negative The difference is that it shows the case where direction information is given. According to this result, for example, in Figures 3 and 5, X(0), X-1(3),
Real pages will be read from X-1(2) and X-1(1). In other words, the actual pages for four consecutive pages in descending order from X(0) are read out. The deviations in Figures 3.6 to 3a8 can be easily understood based on the explanations above.

Referring again to FIG. 1, when the direction information set in the direction information register 2 is positive, the arithmetic unit 3 adds the entire value XKI of the first page sign P, set in the address register 1, and calculates When the direction information is negative, the device 4
1 is subtracted from the value X of the page number P1, and the results of these calculations are supplied to each of the switches 6-9.

The address adjustment port P55 receives the direction information set in the direction information register 2 and the second direction information set in the address register 1.
Based on the page number P2, a switching signal is generated corresponding to the switching devices 6-9 and is supplied to the switching devices 6-9. Switcher 6~
In response to this switching signal, each of 9 selects and accepts either the value X of the first page sign PI and the X+1i calculation from the computing unit 3: , are supplied to conversion buffers 10 to 13, respectively. The fact that the above-mentioned switching signal depends not only on the direction information but also on the value of the second page number P2 means that, for example, in the %3.2 factor, X(1
) are read, whereas 5r, 3. :+In the figure, it is easily understood that X+1(1) is read out.

In the conversion buffers 110 to 13, each switch 6
Real pages are simultaneously read out from the addresses specified by X, X+1 or -X-1 from .about.9 to address registers 14 to 17, respectively.

In the embodiment described above, two arithmetic units 3 and 4 are provided, but only one of them may be used. In that case, the direction information register 2 becomes irrelevant.

In all of the embodiments described above, the translation buffer holds a copy of all address translation data in the address translation table stored in the main memory. However, in the present invention, the translation buffer is stored in the main memory. It also includes those that hold a copy of some address variation data in a certain address conversion table.

According to the present invention, by employing one or more configurations, the selection of pages for which address translation is to be performed is performed based on the page direction and the first page. This is possible at the same time.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIGS. 2 and 3 show an IP for explaining the embodiment. 1.14, 15, 16.17... Address register, 2... Direction information register %3, 4...
...Performance p. device, 5...Address adjustment circuit, 6, 7, 8.9
...Switcher, 10, 11, 12.13...
・・Shunpapa Qin 1 Kuchi LP 2 Jusho 3I Ku Mu 3S Kōritsu 232 diagram Nishi 36 Gen 3 concave Chai 377 Misery 340 Maki 38 Diagram procedure amendment (self-motivated) J・2.1.2r2 1, Display of incident 1982 Patent application No. 223732
No. 2, Name of the invention Address conversion method 3, Relationship with the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: 108 Sumitomo Sanda Building, 37-8 Shiba 5-chome, Minato-ku, Tokyo (Contact address: Kuchimoto Denki Co., Ltd. f1 Kyobe) 5, Subject of amendment (5) Description of “Claims” in the specification (B) Specification Column 6 of the "Detailed Description of the Invention" of the book, Contents of the Amendment (5) Attachment (B) + 1) Page 2] The entry "Sumire" in the first line is corrected to "Simure". (2) The statement “2 pieces” on page 6, line 9 will be corrected to “2 to the 28th power.” (3) The description on page 7, line 5, “Yobi to naru” has been changed to “Yohi 3”.
I am correcting it as follows. (4) The entry “△P” on page 7, line 10 is corrected to [LPJ. (5) The statement “complicated” on page 8, line 11 will be corrected to “conducted.” Agent Patent Attorney Shinji Uchihara 'Attachment Scope of Claims The logical address space that can be accessed by the program is equally divided into pages by the upper N bits of the logical address signal and the N bits following the M bits, and each 2O that stores part or all of the address conversion data on the M multiplier side of 2 for the page whose N bits have the same contents;
N-multiply conversion buffers, at least one arithmetic unit that adds or subtracts 1 from the contents of the N bits, and generates a switching signal corresponding to the conversion buffer based on at least the contents of the N bits. an address adjustment circuit that responds to the switching signal, and a switch corresponding to the conversion buffer that accepts either the contents of the M bits or the output of the arithmetic unit as a search address signal to the conversion buffer; An address conversion method characterized in that real page addresses are allotted all at once to successive pages on the N power side of 2 from the page specified by the logical address signal.

Claims (1)

[Scope of Claims] A program-accessible logical address space is equally divided into pages by the upper M bits of a logical address signal and the N bits following the bits. and a 2 N multiplier side conversion buffer for storing a part or all of the 2 M multiplier side address conversion data for the pages, each of which has the same content of the N bits. at least one arithmetic unit that at least adds or subtracts 1 from the contents of the pit; an address adjustment circuit that generates a switching signal corresponding to the conversion buffer 1 based on at least the content of the N bits; and an address adjustment circuit that receives either the content of the M pit or the output of the arithmetic unit in response to the switching signal to perform the conversion. A switch and a switch corresponding to the conversion buffer 7 which is used as a search address signal to the buffer are provided, and real page addresses are obtained at once for consecutive pages on the N power side of 2 from the page specified by the logical address signal. An address conversion method characterized by the following.