JPS6014331A - Processing system of fixed storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an improvement in a fixed storage device processing method.

(Background technology) In recent years, fixed storage devices (read-only memory) have become popular.

As the capacity of ROM (ROM) increases, the address designation lines (generally address lines) of such fixed storage devices are sometimes arranged in parallel with the intention of improving processing speed, but the increase in the number of address lines There are some notable ones.

For example, for an l megabit ROM, the number of address lines is 19 (219
), resulting in an increase in the wiring capacity of the equipment.

On the other hand, for a central processing unit (CPU), the microinstructions that control it are required to operate at high speed, but data in ROM is not necessarily required to be read at high speed; for example, Information such as Kanji patterns is often determined at mechanical speeds such as output devices such as printers.

(Purpose) The present invention has been made in view of the above points, and its purpose is to allocate microinstructions to the first half of the same ROM, store data in the second half, and receive addresses from the CPU. First output the microinstruction, then output the data on the same line,
An object of the present invention is to provide a fixed storage device processing method that reduces the number of address lines without reducing processing speed.

Here, since the CPU knows whether it is requesting data or instructions when outputting an address, desired ROM information can be read out by changing the timing of reading out.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which R, OMAA
is an address decoder section, RO, which selects seven addresses by receiving the address signal AD from the central processing unit CPU.
M/ is the first R, 0M section in which microinstructions are stored, and ROMt2 is the λth ROM section in which data such as Kanji patterns is stored. O8 is a one-shot circuit that detects switching of the address signal, outputs a level when the address signal changes within a certain period of time, and outputs a high level when it does not change for a certain period of time, and L/ is such a one-shot circuit O8. A latch circuit that latches the ROM 2 output when the output of is high level, OUT is a latch circuit L/(
3) This is an output section that obtains the output of and outputs it on the same line DT.

FIG. 2 is a timing chart showing the operation timing of the device shown in FIG.
Contents A. When -A17 is changing, the one-shot circuit O8 remains at a low level, so that only the microinstruction is output on the data line DT, as shown by the signal D/. On the other hand, if the address signal AD outputs an address with the same content for a certain period of time or more, the one-shot circuit O8 detects this, and the O8 output becomes high level, and the information in ROM-2 becomes ROM/2. Information D/
It will be outputted as soon as possible. Therefore, the central processing unit t C
The PU changes addresses at high speed while executing microinstructions, and when you want to call data, you only have to wait for a certain amount of time before you can call that data, improving processing speed even if you reduce the number of main signal lines. can be done.

(Effect) As is clear from the above, according to the present invention, the microinstruction is allocated to the first half of the ROM (4')-, data is stored in the second half, and the microinstruction is first assigned after receiving the address from the CPU. By outputting the address line and then outputting the data on the same line, it is possible to reduce the number of main address lines without reducing the processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. ROMA...address decoder section, ROM/...microinstruction storage section, R
OM, 2...Data storage section, O8...One-shot circuit, L/...Latch circuit 1 OUT...Output section. Patent applicant: Canon Co., Ltd. <S> Figure 1 Figure 2 AO~AI7 ゜5 1 L

Claims (1)

[Claims] A processing method for a fixed storage device, characterized in that information stored for a plurality of different purposes is outputted in a time-sharing format corresponding to each different purpose according to a designated address.