JPS60176331A - Encoder and decoder - Google Patents

Abstract

PURPOSE:To convert to a code which has prevented ''0'' from continuing, and to send it out, by utilizing exclusive OR of an output of a sum converting circuit, and a clock signal. CONSTITUTION:A code train (In) of an NRZ code inputted from a transmitting code input terminal 14 by synchronizing with a clock signal of a frequency f0 is inputted to one input of an exclusive OR circuit 15, a signal which has delayed an output of the exclusive OR circuit 15 by a one bit period by a one bit delaying circuit 16 is inputted to the other input, a sum converting output signal Sn is obtained, this signal and a clock signal C of the frequency f0 and 50% duty ratio is inputted to an exclusive OR circuit 18, and a transmitting output signal is obtained. A decoder is constituted of an exclusive OR circuit and a difference converting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an encoder for converting and outputting a transmission code into a code format suitable for transmission in an optical fiber transmission system, a coaxial transmission system, a data link, etc.; The present invention relates to a decoder that receives a signal sent to a transmission path by a transmitter and restores it to the original transmission code.

In various conventional transmission systems, various code conversions have been devised to prevent timing information from being lost due to consecutive zero codes and to ensure code transmission characteristics. It is well known that one of them is the DMI code. This means that "1.0" or "0.1" is sent out alternately at half the bit interval for "l" of the transmission data, and '1.1' for "O" of the transmission data. ” or “o, o”
are sent out alternately, and the receiving side decodes the received DMI code into the original transmission data.

FIG. 1 and FIG. 2 are circuit diagrams showing an example of a conventional DMI encoder and its decoder, respectively. That is,
As shown in FIG. 1, the transmission code string In is input from the transmission code input terminal l in synchronization with the clock signal of frequency f0.
(NRZ code), the frequency fo input from the f0 clock input terminal 2, and the clock signal C with a duty of 50%.
is input to the NOR circuit 3, and the output signal of the NOR circuit 3 and 2f, the frequency 2f input from the clock input terminal 4, and the clock signal C2 of 50% of the tutee are input to N0.
By manually inputting the Ru path 5, the output signal of the NOR circuit 5 is
The 2 frequency divider 6 is operated manually, and the signal sequence Xn converted into a DMI code by the output of the 172 frequency divider 6 is sent out to the transmission line via the DMI code output terminal 7.

As shown in FIG. 2, the decoder on the receiving side receives the received signal string Xn input from the DMI code input terminal 8 and delays the received signal string Xn by one hit period (frequency 2f0) by a 1-bit delay circuit 9. The output signal G of the exclusive OR circuit 10 is input to the exclusive OR circuit 10 and the output signal G is converted into a difference signal formed by the one hit I/delay circuit 11 and the The conversion circuit performs differential conversion once more, and the output of the exclusive OR circuit 12 restores the original transmission code, which is output from the decoded signal output terminal 13.

FIGS. 3A to 3J are time charts showing signals of each part of a conventional encoder and decoder. Same figure (
A) is the transmission code string In input from the transmission code input terminal l.
, and (13) in the same figure shows the clock signal C of frequency f0 input from the f0 clock input terminal 2, and (C) in the same figure shows
shows the inverted clock signal C', and (D) in the same figure shows the inverted clock signal C'.
The output signal of the R circuit 3 is shown in FIG.
2, (F) in the figure shows the output signal of the NOR circuit 5, and (CG) in the same figure shows the DMI signal output from the DMI code output terminal 7.
A converted signal sequence Xn is shown. In this case, if the clock signal input from the f0 clock input terminal 2 is an inverted clock signal C' as shown in FIG.
The code string Xn' sent out from the DMI code output terminal 7 is an inverted version of the code string Xn shown in (G) of the same figure, as shown in FIG.

Figure (I) shows that the code string Xn or Xn' is D (in Figure 2).
The output signal G of the υ11 transitive OR circuit jO when input from the MI' code input terminal 8 is shown. In other words, D in Figure 1
Even if the phase of the clock signal C is reversed in the MI encoder, the output signal G of the exclusive OR circuit 10 of the decoder in FIG.
are the same. Then, at the output of the Sugi1 alistic OR circuit 12, a decoded signal H as shown in (J) of the same figure appears.

The conventional encoder described above has the disadvantage that it is necessary to process the transmitted code using the clock signal C2 of twice the frequency, which is disadvantageous in terms of operating speed. Also, in the decoder,
Since it is necessary to perform differential conversion twice in order to eliminate uncertainty in the output, there is a drawback that the circuit scale becomes large.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide a clock signal with a frequency twice that of the transmitted code.
The object of the present invention is to provide an encoder and a decoder that can convert the code into a code that prevents continuity and send it out, and that can reliably restore the original code on the receiving side.

Structure of the Invention The encoder of the present invention includes a summation conversion circuit that performs summation conversion of a manually generated transmission code in synchronization with a clock signal, and a υ1-alternative logic between the output signal of the summation conversion circuit and the clock signal. The present invention is characterized by comprising an exclusive OR circuit that outputs a sum.

Further, the decoder of the present invention includes an exclusive OR circuit that inputs an input signal and a clock signal, and a difference conversion circuit that differentially converts an output signal of the exclusive OR circuit. It is characterized in that the original code obtained by decoding the input signal is obtained by the output of the input signal.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 4 is a circuit diagram showing an encoder according to an embodiment of the present invention. That is, the code string In of the NRZ code inputted from the transmission code input terminal 14 in synchronization with the clock signal of frequency f0 is inputted to one input of the exclusive OR circuit 15,
The other input of the exclusive OR circuit 15 is supplied with a signal obtained by delaying the output of the exclusive OR circuit 15 by a 1 bit period by a 1 bit delay circuit 1G. The exclusive OR circuit 15 and the 1-bit delay circuit 18 constitute a sum conversion circuit. The output signal Sn of the summing conversion circuit and the frequency f0 which is also input to the f0 clock input terminal 17
, and the clock signal C with a 50% duty ratio are input to the exclusive OR circuit 18, and the exclusive OR circuit 18 calculates the exclusive OR of both inputs and outputs the result to the transmission signal output terminal 18. The signal string Xn that is also output from the transmission signal output terminal 18 is a code string that is prevented from being continuous. This embodiment has an advantage in operating speed because it does not need to operate with a clock of 1 frequency 2f unlike the conventional encoder shown in FIG.

FIG. 5 is a circuit diagram showing a decoder according to an embodiment of the present invention. That is, the code string Xn input from the received signal input terminal 20 and the clock signal C of frequency f0 input from the f0 clock input terminal 21 are input to the exclusive OR circuit 22, and the output of the exclusive OR circuit 22 is The signal Rn is differentially converted by a difference conversion circuit consisting of an exclusive OR circuit 24 and an l-bit delay circuit 23, and is converted into the original code string I.
Restore n. This decoder has the effect of simplifying the circuit because it does not perform differential conversion twice as in the conventional example shown in FIG.

Next, the operation of this embodiment will be explained with reference to FIG. FIG. 6 is a time chart showing signals of each part in the above embodiment. Now, when the NRZ code string In as shown in FIG. 6(A) is input to the exclusive OR circuit 15,
The output of the exclusive OR circuit 15, ie, the output signal Sn of the sum conversion circuit, is as shown in FIG. This code string Sn and the frequency f as shown in the same figure (C). The exclusive OR with the clock signal results in a code string Xn as shown in FIG. When this No. 94 column Xn is input to the receiving side decoder shown in FIG. 5, the output Rn of the exclusive OR circuit 22 becomes as shown in FIG. 6(F). Therefore, the code string In obtained by differentially converting the signal becomes as shown in FIG. This is the same as the original transmission code string. Here, the phase synchronization of the encoder and decoder clock signals is 180°
When the clock signal C' input to the exclusive OR circuit 18 shifts as shown in FIG. 6(D), the output Rn' of the υ1 passive OR circuit 22 becomes as shown in FIG. As shown in , the fq sequence is obtained with the polarity of Rn inverted.

However, the signal obtained by differentially converting the code string Rn' is still shown in (H) in the same figure, and the code string on the transmitting side is correctly decoded. Therefore, if the gradient encoder and decoder of this embodiment are used, there is no need to perform clock phase detection control and no additional circuit is required, resulting in a significant simplification of the circuit.

Effects of the Invention As described in 1-, in the present invention, the encoder is configured to output the logical OR of the signal obtained by adding and converting the transmission code string and the clock signal, and on the receiving side, the input (Since the decoder is configured to restore the original right code sequence by differentially converting the signal obtained by taking the exclusive OR of the M code and the clock signal, if this encoder and decoder are used, Correct decoding is possible even if the phase of the clock signal between the encoder and decoder is reversed.Therefore, there is no need for a complicated circuit to detect the phase of the clock and output the correct information code string. This has the effect of correctly transmitting information with a simple circuit.Furthermore, both the encoder and decoder of the present invention are operated by a clock signal having the same frequency as the bit interval of the transmission code string. , it is not necessary to use a clock signal of twice the frequency as in the conventional case, and the operating speed is extremely advantageous.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional DMI encoder, Figure 2 is a circuit diagram showing an example of a conventional DMI encoder;
FIG. 3 is a circuit diagram showing an example of a conventional DMI decoder, FIG. 3 is a time chart showing various signals of the conventional example, FIG. 4 is a circuit diagram showing an embodiment of the encoder of the present invention, and FIG. 6 is a circuit diagram showing one embodiment of the decoder of the present invention, and FIG. 6 is a time chart 1 showing signals of various parts of the above embodiment. In the figure, 1: transmission code input terminal, 2: f0 clock input terminal, 3: NOR circuit, 4: 2f. Crochet input terminal, 5: NO'R circuit, 6: 1/2
Frequency divider, 7nDMI gradient output terminal, 8: DMI sign input terminal, 9. If: 1-bit delay circuit, 10°+2.
15.18, 22, 24: Exclusive OR circuit, 132 decoded signal output terminal, 14: Transmission code input terminal, 18.23
=1-bit delay circuit, 17, 21:, f, clock input terminal, 19: transmission signal output terminal, 20: reception signal input terminal, 25: decoded signal output terminal. Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney Toshimune Sumita Figure 1; /3' 201

Claims (2)

[Claims] (1) A summation conversion circuit that performs summation conversion of a transmission code input in synchronization with a clock signal, and an exclusive OR that outputs an exclusive OR of the output signal of the summation conversion circuit and the clock signal. An encoder characterized by comprising a circuit. (2) An exclusive OR circuit that manually inputs an input signal and a clock signal, and a differential conversion circuit that differentially converts the output signal of the exclusive OR circuit, and converts the input signal by the output of the differential conversion circuit. A decoder characterized in that it obtains a decoded original code.