JPS60186071A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60186071A JPS60186071A JP59041607A JP4160784A JPS60186071A JP S60186071 A JPS60186071 A JP S60186071A JP 59041607 A JP59041607 A JP 59041607A JP 4160784 A JP4160784 A JP 4160784A JP S60186071 A JPS60186071 A JP S60186071A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- semiconductor device
- mesa groove
- mesa
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
Landscapes
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 イ、産業上の利用分野 不発明は、半導体装置の製造方法に係り、特に。[Detailed description of the invention] B. Industrial application field The invention relates particularly to a method of manufacturing a semiconductor device.
メサ構造を有する半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device having a mesa structure.
口、従来技術
従来、ＰＮ接合を形成し、メサ溝を形成した後は、高温
の熱処理を施すことはなく、メサ溝形成の際、ＰＮ接合
のメサ溝への露出部は凸部を残し、特に悪影響を与える
等の欠点があった。すなわち。Conventionally, after forming a PN junction and forming a mesa groove, high-temperature heat treatment is not performed. In particular, there were drawbacks such as adverse effects. Namely.
第１図は従来のメサ構造を有する半導体装置の断面図で
ある。第１図において、１は、−導電、型。FIG. 1 is a sectional view of a conventional semiconductor device having a mesa structure. In FIG. 1, 1 indicates -conductivity, type.
例えばＮ型の半導体基板、２は、基板１に不純物拡散に
よ膜形成されたＰ層、３は、２層２の形成後、メサエッ
チングによ膜形成されたメサ溝の内壁である。メサ溝内
壁３には、ＰＮ接合５の接合端６が露出するが、ガラス
被膜＋によシ被われ保護されている。しかし、接合端６
はメサ溝形成の時に凸状となシ、ＰＮ接合５に逆バイア
スを印加したとき、凸部近傍の電界が強くなり、逆耐圧
が低下する欠点があった。For example, an N-type semiconductor substrate, 2 is a P layer formed on the substrate 1 by impurity diffusion, and 3 is an inner wall of a mesa groove formed by mesa etching after the formation of the second layer 2. The joint end 6 of the PN junction 5 is exposed on the inner wall 3 of the mesa groove, but it is covered and protected by a glass coating +. However, the joint end 6
However, when a reverse bias is applied to the PN junction 5, the electric field in the vicinity of the convex portion becomes strong and the reverse breakdown voltage decreases.
／・１発明の目的
本発明の目的は、メサ溝内壁の、ＰＮ接合の接合端露出
部の形状が滑らかであって、耐圧特性のよいメサ構造を
有する半導体装置の製造方法を提供するにある。/.1 Purpose of the Invention An object of the present invention is to provide a method for manufacturing a semiconductor device having a mesa structure with a smooth shape of the exposed portion of the PN junction on the inner wall of the mesa groove and good withstand voltage characteristics. .
二０発明の構成
本発明によれば、半導体基板にＰＮ接合を形成後、メサ
溝を形成し、さらに熱処理を施して、前記メサ溝内壁に
露出したＰＮ接合端の位置を元の位置より移動させるこ
とを含む半導体装置の製造方法が得られる。20 Structure of the Invention According to the present invention, after forming a PN junction in a semiconductor substrate, a mesa groove is formed, and further heat treatment is performed to move the position of the PN junction end exposed on the inner wall of the mesa groove from its original position. A method of manufacturing a semiconductor device is obtained.
ホ、実施例 つぎに本発明を実施例によシ説明する。E, Example Next, the present invention will be explained using examples.
第２回は本発明の一実施例方法により製造された半導体
装置の断面図である。第２図において、点線で示す当初
のＰＮ接合５の接合端が露出したメサ溝内壁３の露出部
６は凸状を呈しているが、メサ溝内壁を低温形成の従来
のガラス被膜の代わりに、高温形成の鉛ガラスの被膜４
ａで被い、それから、高温の熱処理を行っている。この
熱処理により、２層２の不純物が内部に拡散し、ｐＮ接
合は実線で示す７の位置まで移動する。その結果ｐＮ接
合の接合端は、当初の接合端の位置６より離れ、滑らか
な内壁面に露出することになる。The second part is a cross-sectional view of a semiconductor device manufactured by a method according to an embodiment of the present invention. In FIG. 2, the exposed portion 6 of the mesa groove inner wall 3 where the bond end of the original PN junction 5 is exposed, shown by the dotted line, has a convex shape. , high temperature formed lead glass coating 4
After that, it is coated with A and then subjected to high-temperature heat treatment. By this heat treatment, the impurities in the second layer 2 are diffused inside, and the pN junction moves to the position 7 shown by the solid line. As a result, the junction end of the pN junction is separated from the original junction end position 6 and exposed to the smooth inner wall surface.
第３図は第２の実施例による半導体装置の断面図である
。第３図において、当初のｐＮ接合５の接合端の露出部
凸状６を形成しているが、この状態で、酸化雰囲気中で
熱処理を行い、メサ溝内壁３に酸化被膜８を設け、６の
凸部を緩和すると同時に、第１の実施例と同様に、ＰＮ
接合面を当初の位置５から７へ移動させることができる
。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment. In FIG. 3, a convex shape 6 is formed at the exposed end of the original pN junction 5. In this state, a heat treatment is performed in an oxidizing atmosphere to form an oxide film 8 on the inner wall 3 of the mesa groove. At the same time, as in the first embodiment, the PN
The joint surface can be moved from the original position 5 to 7.
へ８発明の効果
この様にして、本発明によれば、メサ溝形成時に、発生
した当初のＰＮ接合の接合端が露出する凸部の位置から
、熱処理を施すことによってｐＮ接合を移動させ、よっ
て、接合端露出部凸状のための電界強度の増加による耐
圧低下の欠点をなくし、耐圧特性のよい半導体装置を製
造可能とする。In this way, according to the present invention, when forming a mesa groove, the pN junction is moved from the position of the convex part where the junction end of the originally generated PN junction is exposed by performing heat treatment, Therefore, the drawback of a decrease in breakdown voltage due to an increase in electric field intensity due to the convex shape of the exposed portion of the junction can be eliminated, and a semiconductor device with good breakdown voltage characteristics can be manufactured.
第１図は従来のメサ構造を有する半導体装置の断面図、
第２図は本発明の一実施例による半導体装置の断面図、
嬉３図は本発明の他の実施例による半導体装置の断面図
である。
１・・・・・・Ｎ型基板Ｎ層、２・・・・・・Ｐ型拡散
層、３・・・・・・メサ溝内壁、４・・・・・・低温ガ
ラス被膜、４ａ・・・・・・高温ガラス被膜、５・・・
・・・当初のＰＮ接合、６・・・・・・ＰＮ接合端露出
部の凸起、７・・・・・・移動後のＰＮ接合、８・・・
・・・酸化膜。
躬１区
第３図FIG. 1 is a cross-sectional view of a conventional semiconductor device having a mesa structure.
FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention;
Figure 3 is a sectional view of a semiconductor device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... N-type substrate N layer, 2... P-type diffusion layer, 3... Mesa groove inner wall, 4... Low-temperature glass coating, 4a... ...High temperature glass coating, 5...
... Initial PN junction, 6... Protrusion of exposed part of PN junction end, 7... PN junction after movement, 8...
···Oxide film. 1st Ward Map 3
Claims (1)
装置の製造方法において、前記メサ溝を形成した後に、
該メサ溝に露出したＰＮ接合部を熱処理等によシ当初の
位置よシ移動させることを特徴とする半導体装置の製造
方法。[Claims] A mesa groove is provided in a semiconductor substrate on which a PN junction is formed. In this method of manufacturing a semiconductor device having a structure in which the inner wall of the mesa groove is covered with glass, after forming the mesa groove,
A method for manufacturing a semiconductor device, characterized in that the PN junction exposed in the mesa groove is moved from its original position by heat treatment or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59041607A JPS60186071A (en) | 1984-03-05 | 1984-03-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59041607A JPS60186071A (en) | 1984-03-05 | 1984-03-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60186071A true JPS60186071A (en) | 1985-09-21 |
Family
ID=12613044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59041607A Pending JPS60186071A (en) | 1984-03-05 | 1984-03-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60186071A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4740477A (en) * | 1985-10-04 | 1988-04-26 | General Instrument Corporation | Method for fabricating a rectifying P-N junction having improved breakdown voltage characteristics |
| US4980315A (en) * | 1988-07-18 | 1990-12-25 | General Instrument Corporation | Method of making a passivated P-N junction in mesa semiconductor structure |
| US5166769A (en) * | 1988-07-18 | 1992-11-24 | General Instrument Corporation | Passitvated mesa semiconductor and method for making same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50110571A (en) * | 1974-02-07 | 1975-08-30 | ||
| JPS5291385A (en) * | 1976-01-26 | 1977-08-01 | Nec Corp | Semiconductor device |
| JPS54109779A (en) * | 1977-12-10 | 1979-08-28 | Itt | Method of fabricating semiconductor |
-
1984
- 1984-03-05 JP JP59041607A patent/JPS60186071A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50110571A (en) * | 1974-02-07 | 1975-08-30 | ||
| JPS5291385A (en) * | 1976-01-26 | 1977-08-01 | Nec Corp | Semiconductor device |
| JPS54109779A (en) * | 1977-12-10 | 1979-08-28 | Itt | Method of fabricating semiconductor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4740477A (en) * | 1985-10-04 | 1988-04-26 | General Instrument Corporation | Method for fabricating a rectifying P-N junction having improved breakdown voltage characteristics |
| US4980315A (en) * | 1988-07-18 | 1990-12-25 | General Instrument Corporation | Method of making a passivated P-N junction in mesa semiconductor structure |
| US5166769A (en) * | 1988-07-18 | 1992-11-24 | General Instrument Corporation | Passitvated mesa semiconductor and method for making same |
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