JPS60200570A - Electronic device - Google Patents

Abstract

PURPOSE:To obtain an electronic device which has excellent heat resistance, corrosion resistance, and bondability in high reliability by forming electrodes made of a material having corrosion resistance and high heat resistance in the lowermost layer and made of a material having small electric resistance in the other layer and preferable bondability on the uppermost layer on the main surface of a compound semiconductor substrate. CONSTITUTION:A Schottky barrier junction electrode formed on the main surface of a compound semiconductor substrate is formed at the lowermost layer of a material having corrosion resistance and high heat resistance, and other layer is formed of a material having small electric resistance and preferable bondability in the uppermost layer in a multilayer structure. For example, the gate electrode of a GaAs Schottky barrier gate field effect transistor is formed in a 2-layer structure, a W layer 11 having heat resistance and excellent corrosion resistance is formed directly on the main surface of a GaAs substrate 8, and an aluminum layer 18 having inexpensive electric resistivity and low cost material and excellent bondability is formed on the layer 11. Thus, the heat resistance and the corrosion resistance of the electrode are improved, the bondability of the wirings is improved, thereby obtaining a field effect transistor having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to electronic devices, particularly electronic devices having Schottky barrier junction electrodes, such as Schottky barrier field effect transistors.

[Background technology]

A gallium arsenide field-effect transistor (GaAs-ME S-FET) is a microwave transistor with features such as low noise, high cut-off frequency, and high output.The gallium arsenide field effect 1-transistor (GaAs-ME S-FET) is formed based on a substrate with a zinc blende crystal structure. is widely known. In addition, as one of these GaAs-MES FETs, a Schottky barrier gate field effect transistor (S
BG-FET). 5BG-FET has an ohmic contact structure source provided on the main surface of the n-conductivity type active region,
It consists of a drain electrode and one or two Goo 1-electrodes of Schottky junction structure provided in between, forming a single gate structure or a dual Goo 1-structure. By the way, in the field effect transistor,
Goo 1 - The material constituting the electrode is, for example, an electronic material,
As described in April 1980, pp. 74-78 (Microwave Transistor), aluminum (A
Q) Also, fractrimetal is the mainstream. As described in the same document, in terms of reliability, AI2 is the most stable, at least as long as the element (chip) is hermetically sealed.

Incidentally, for products whose product costs are being reduced, the mainstream is a resin package, which has a low packaging cost and is suitable for mass production.

However, the inventor of the present invention has revealed that a product using tungsten (W), which is AQ or Riff Raff 1 to Remetall, as a gate electrode and having a resin package as a package has a reliability problem.

In other words, when this type of resin package product is subjected to a forced reverse bias test, it is found that the silicon device MO
Characteristics deteriorate in about half the time of the S-FETjlu product. When the inside of such defective products is disassembled and examined, it is found that in most of them, the AQ forming the gate electrode is corroded or has completely disappeared. This means that if a resin packaged product is used in a bad environment, its characteristics will deteriorate early, which is unfavorable in terms of reliability. On the other hand, it is also possible to use W as an electrode, but since W is a refractory metal (highly heat-resistant material), it has excellent heat resistance and corrosion resistance, but if it is made of gold (Au), it will not work as a wire. This is undesirable because it has problems such as poor connection, lower bondability reliability, lower yield, and poor mass productivity.

[Purpose of the invention]

An object of the present invention is to provide a highly reliable electronic device with excellent heat resistance, corrosion resistance, bondability, etc.

Another object of the present invention is to provide an inexpensive electronic device with excellent mass productivity.

The above and other objects and novel features of the present invention include:
It will be clear from the description herein and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the GaAs barrier gate field effect transistor of the present invention, the gate electrode has two layers, and the W layer, which has excellent heat resistance and corrosion resistance, is formed directly on the main surface of the GaAs substrate. In addition, the A2 layer, which has low electrical resistivity, low material cost, and excellent bondability, is formed on this W layer, which improves the heat resistance and corrosion resistance of the electrode, and improves the bondability with the wire. Since the stability is also improved, a highly reliable field effect transistor can be provided. Further, since AQ having low electrical resistance is used, characteristics can be improved.

Furthermore, the manufacturing cost of field effect transistors can be reduced by using AQ with low material cost and by improving mass productivity due to improved bondability.

〔Example〕

FIG. 1 is a plan view schematically showing a GaAs Schottky barrier gate field effect transistor chip according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 6 is a cross-sectional view showing the manufacturing state, FIG. 3 is a cross-sectional view of the wafer after mesa etching in chip manufacturing, FIG. 4 is a cross-sectional view of the wafer after the diffusion process, and FIG. 5 is the same. FIG. 6 is a cross-sectional view of the wafer after forming source and drain electrodes, and FIG. 6 is a cross-sectional view of the wafer after forming gate electrodes.

The GaAs Schottky barrier gate field effect transistor chip (hereinafter simply referred to as a chip) of this embodiment has one gate between a source electrode 1 and a drain electrode 2, as shown in FIGS. 1 and 2. It has a single goo structure with an electrode 3 provided. Note that in FIG. 1, the passivation film 5 shown in FIG. 2, which partially covers the surface of the element (chip) 4, is omitted. In addition, the area framed by the two-dot chain line shown in FIG. 1 is the bonding pad area 6 of each electrode.
This region is a region not covered by the passivation film 5, and 1. This is a region to which a wire disposed between the chip 4 and the outside is connected.

The chip 4 undergoes the steps shown in FIGS. 3 to 6 to become the chip 4 shown in FIGS. 1 and 2.

Hereinafter, manufacturing of the chip 4 will be explained with reference to these figures.

First, as shown in FIG. 3, a compound semiconductor thin plate (wafer) 7 is prepared. This wafer 7 is a semi-insulating Ga
An epitaxial layer 9 having a thickness of, for example, about 1 μm is provided on the main surface of a substrate 8 made of As. This epitaxial layer 9 is of n-type.

Further, the main surface of this wafer 7 is partially etched, and mesa portions 10 are provided in the form of islands.

The etching is carried out deeper than the epitaxial layer 9, and the mesa portion 10 forms a strand.

Next, a W layer 11 having a thickness of approximately 100 OA to 1 μm is formed on the main surface of the substrate 8 at the mesa portion 10 and its periphery by conventional photolithography and vapor deposition methods. This W layer 11 becomes the lower layer constituting the goo 1 to the electrode 3, and as shown in FIG. It has a pattern having a rectangular bonding area (pad) 12 at its tip.

Next, as shown in FIG. 4, silicon is implanted into the main surface of the mesa portion 10 as a mask for the W layer 11, and an n+ type ohmic contact layer 1 with a depth of about 0.5 μm is implanted.
2 is formed.

Next, as shown in FIG. 5, a phosphorus glass film (referred to as PSG film) 13 is formed over the entire main surface of the wafer 7, and a PSG film is formed in the region where the source electrode 1 and the drain electrode 2 are to be formed. Three portions of one film portion are removed, and a source electrode 1 and a drain electrode 2 are formed in the removed portions (contact holes) by conventional photolithography, vapor deposition, and lift-off methods. Both electrodes have the same configuration,
For example, A u -G e where the bottom layer is 1300A thick
layer 14, having a thickness 30 formed on the Au-Ge layer 14;
0A Ni layer 15. Thickness 45 formed on Ni layer 15
00A, and an uppermost Au layer 16.

Next, as indicated by J in FIG. 6, a photoresist film 17 is formed over the entire main surface of the unihaf, and a portion corresponding to the W layer 11 is formed on this photoresist film 17 by a commonly used lithography technique. The AQ layer 18 is deposited on the removed portion.

Formed by partial etching. This AQ layer 18 cannot be made too thick because patterning properties will be poor if it is too thick, but if it is too thin, the effect of lowering the electrical resistance of the electrode 3 to the gate 1 and the bondability with the wire will deteriorate, so it should be set to the minimum value. For example, about 0.5 μm is required.

After that, the entire main surface of the wafer 7 is passivated 1 and 5.
At the same time, the passivation film 5 in the portions where the bonding pads are to be formed is removed using a commonly used photolithography method to expose the bonding pads 19 of each electrode, and the wafer 7 is divided into lattice shapes. Then, a chip 4 as shown in FIG. 2 is manufactured.

Such a chip 4 is fixed to a support plate, each bonding pad 19 and the inner end of a lead serving as an external terminal is connected by a wire, and further sealed with a resin package to form a field effect transistor.

〔effect〕

(20) In the field effect transistor of the present invention, the gate electrode 3 has a two-layer structure consisting of W and AQ.

Since heat-resistant and corrosion-resistant W is in direct contact with the GaAs substrate, the gate electrode 3 has excellent heat resistance and corrosion resistance, and the reliability of the transistor is increased.

2. The upper layer of the gate electrode 3 is made of AQ, which has low electrical resistivity, good bondability with wires, and low material cost. Therefore, the mutual conductance is improved by reducing the electrical resistivity of the gate electrode 3, and the high frequency characteristics are improved.

3. From 2 above, since the surface of the gate electrode 3 is exposed with AM having good bondability with the wire, the reliability of the connection with the wire is improved, which improves the manufacturing yield and thereby improves mass productivity. Improvements can be achieved.

4. From 2 above, the gate electrode 3 is made of A with low material cost.
Since Q is used, the cost of Goo 1-electrode 3 can be reduced.

5. With 1 to 4 above, a synergistic effect is obtained in that a highly reliable GaAs Schottky barrier gate field effect transistor can be provided at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, gate electrode 3
The underlying layer is other riffraff 1-remetalls, such as Cy,
Similar results can be obtained using metals such as Mo. Especially M
o has good workability and is therefore suitable for finer patterns.

Further, as shown in FIG. 7, when forming the source electrode 1 and the drain electrode 2, the PSG film 1 covering the W layer 11 is removed and the source electrode 1 and electrode 3 are placed on the Wll. Similar to drain electrode 2, A u -G
cN L 4 , N i N l 5 , A u
lfl 16 may be formed. This structure has the advantage that the number of steps for forming the layer constituting the gate electrode 3 formed on the WJWII is reduced compared to the above embodiment. In addition, in this structure, the top layer of the goo 1-electrode 3 is made of Au with good bondability.
As a result, it is possible to improve the reliability of bonding and thereby improve mass production.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the manufacturing technology of Schottky barrier gate type field effect transistors, which is the background field of application, but the invention is not limited to this. For example, it can be applied to manufacturing techniques for ICs and the like incorporating Schottky barrier gate field effect transistors.

The present invention is applicable to at least electronic devices having Schottky barrier junction electrodes.

[Brief explanation of the drawing]

FIG. 1 is a plan view schematically showing a GaAs Schottky barrier gate field effect transistor chip according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1, and FIG. FIG. 4 is a cross-sectional view of a wafer after mesa etching in chip manufacturing; FIG. 5 is a cross-sectional view of a wafer after a diffusion process in chip manufacturing; and FIG. 5 is a source in chip manufacturing. FIG. 6 is a cross-sectional view of a wafer with a drain electrode type formed thereon. FIG. 6 is a cross-sectional view of a wafer after forming a gate electrode in chip manufacturing. FIG. 7 is a GaAs Schottky barrier gate 1 to field effect transistor according to another embodiment of the present invention. FIG. 3 is a cross-sectional view showing the manufacturing state of the chip. ■... Source electrode, 2... Drain electrode, 3...
Gate electrode, 4... Chip, 5... Passivation film, 6... Ponding pad region, 7... Compound semiconductor thin plate (wafer), 8... Substrate, 9... Epitaxial layer, IO ... Mesa part, 11 ... W layer, 1
2... Ohmic contact layer, 13... PSG film (phosphorus glass film) 14--Au-Ge layer, 15-Ni layer, 16 = Au layer, 17... Photoresist film, 1
8... AQ layer, 19... Ponding pad. Agent Patent Attorney Akio Takahashi Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. An electronic device having an electrode formed by Schottky barrier junction on the main surface of a compound semiconductor substrate, wherein the electrode has a multilayer structure, and the bottom layer is made of a material having corrosion resistance and high heat resistance. 1. An electronic device characterized in that the other layers are made of a material having low electrical resistance and the uppermost layer is made of a material having good bondability. 2. The electrode is the electrode of a field effect transistor formed on the main surface of the GaAs substrate, and the electrode is directly connected to the GaAs substrate.
2. The electronic device according to claim 1, comprising a layer made of W or Cr formed on the main surface of As, and a layer made of AQ formed on this layer.