JPS6128228B2 - - Google Patents

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Publication number
JPS6128228B2
JPS6128228B2 JP51096053A JP9605376A JPS6128228B2 JP S6128228 B2 JPS6128228 B2 JP S6128228B2 JP 51096053 A JP51096053 A JP 51096053A JP 9605376 A JP9605376 A JP 9605376A JP S6128228 B2 JPS6128228 B2 JP S6128228B2
Authority
JP
Japan
Prior art keywords
electrode
conductor layer
bonding
ohmic
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51096053A
Other languages
Japanese (ja)
Other versions
JPS5322362A (en
Inventor
Susumu Takahashi
Fumio Murai
Nao Sato
Katsutoshi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9605376A priority Critical patent/JPS5322362A/en
Priority to NL7609676A priority patent/NL7609676A/en
Priority to DE2639373A priority patent/DE2639373B2/en
Priority to GB36641/76A priority patent/GB1509160A/en
Publication of JPS5322362A publication Critical patent/JPS5322362A/en
Publication of JPS6128228B2 publication Critical patent/JPS6128228B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置において電極と該電極に対
するワイヤボンデング部等の外部引出導体取付部
の構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of an electrode and an external lead conductor attachment part such as a wire bonding part to the electrode in a semiconductor device.

従来のオーム性接触電極の構造は第1図に示し
たように、半導体結晶12上に設けたオーム性接
触電極を組立外部引出導体取付部用領域とするも
ので、両者が共存共通になつている。このような
オーム性接触電極構造は次のような欠点を有して
いる。(1)オーム性電極とボンデング領域の共存に
より、ボンデング作業時の力による素子特性劣化
が起る。(2)ボンデング領域共存のため、実質的オ
ーム性電極の面積が広くなり、素子特性の劣化が
起る。(1)についてはボンデング時の力が加わるこ
とによる能動層領域への半導体結晶ひずみ、抵抗
増大がある。(2)については寄生素子となる容量、
抵抗成分が面積増大と共に大きくなる。特に、高
い周波数で動作させたり、高速スイツチング動作
させる素子では寄生素子軽減は高性能化のため最
とも重要な要素となる。
As shown in Fig. 1, the structure of the conventional ohmic contact electrode is such that the ohmic contact electrode provided on the semiconductor crystal 12 is used as the area for attaching the assembled external lead conductor, so that both coexist and become common. There is. Such an ohmic contact electrode structure has the following drawbacks. (1) Due to the coexistence of the ohmic electrode and the bonding region, the device characteristics deteriorate due to the force during the bonding process. (2) Due to the coexistence of the bonding region, the area of the substantial ohmic electrode increases, resulting in deterioration of device characteristics. Regarding (1), there is strain in the semiconductor crystal in the active layer region and an increase in resistance due to the force applied during bonding. Regarding (2), the capacitance that becomes a parasitic element,
The resistance component increases as the area increases. Particularly in devices that operate at high frequencies or perform high-speed switching operations, reducing parasitic elements is the most important factor for improving performance.

本発明は上述の従来技術の欠点をなくし、オー
ム性電極の特性向上が計れ、寄生素子の少ないか
つ接続が良好な電極構造を提供するものである。
The present invention eliminates the above-mentioned drawbacks of the prior art, and provides an electrode structure with improved characteristics of ohmic electrodes, fewer parasitic elements, and good connections.

すなわち、本発明では、特願昭50−105897号で
述べた様に、電極と該電極のボンデングパツドを
分離し、両者を相互に接続するものであり、特
に、オーミツク電極部分に上記手法を適用したも
のである。
That is, in the present invention, as described in Japanese Patent Application No. 50-105897, the electrode and the bonding pad of the electrode are separated and the two are connected to each other. In particular, the above method is applied to the ohmic electrode portion. It is something.

本発明の構成要件は次のようなものである。第
1のオーム性電極ともう1つ別な機能、例えばボ
ンデング領域と分離して設ける。第2にオーム性
電極とボンデング領域のような別の機能のものと
の接触は半導体装置上に被着した別の金属で接続
する。このとき、ボンデング領域全面に別の金属
を被着しても良い。第3に、各電極部分の対向し
ている部分の形状は接続良好にするため、金属の
接触りよう線を多くするため、凸部又凹部にす
る。当然の事ながら、オーム性電極は寄生素子を
小さくし、且つ素子動作上支障のない様な面積と
する。
The constituent elements of the present invention are as follows. It is provided separately from the first ohmic electrode and another function, such as a bonding region. Second, the contact between the ohmic electrode and another function, such as a bonding area, is made with another metal deposited on the semiconductor device. At this time, another metal may be applied to the entire surface of the bonding area. Thirdly, the opposing portions of each electrode are shaped into convex or concave portions in order to increase the number of metal contact lines for good connection. Naturally, the area of the ohmic electrode should be such that the parasitic elements are small and the area does not interfere with the operation of the element.

これら3つの要件を満たす電極構造をシヨツト
キ接合型電界効果トランジスタを例にとつて第2
図に示した。基板11上に設けられた能動層12
上にソース13、ドレイン14、ゲート電極15
がある。このときソース13、ドレイン14はオ
ーム性接触電極で、ボンデング領域をそれぞれの
電極に対応してソース電極用ボンデング領域1
3′、ドレイン電極用ボンデング領域14′が設け
られている。その接続はこの場合はゲート金属1
5で接続されている(もちろん、他の金属で接続
しても良いが、ゲート金属15を用いることが工
程上有利である)。その平面図は第3図に示す。
第3図でソース電極13、ドレイン電極14との
対向して設けてあるボンデング領域13′,1
4′部分は他の金属15′によつて接続する時、接
続断線を起させないため凹,凸形状に形成する。
すなわち、接続部には段差があることから、ある
断線確率が存在するが、このように凹,凸形状と
することによつて増えた接触りよう線の分だけ金
属15′に対する接続部の長さを多くすることが
でき、これにより電極13,14およびボンデン
グ領域13′,14′と、金属15′の接続性が向
上する。尚、このとき、ボンデング領域を接続用
金属15′で全面を覆う事は可能で、そのとき、
少なくとも最上部の金属はボンデング可能な金属
にする必要がある。
The second example of an electrode structure that satisfies these three requirements is a Schottky junction field effect transistor.
Shown in the figure. Active layer 12 provided on substrate 11
Source 13, drain 14, gate electrode 15 on top
There is. At this time, the source 13 and drain 14 are ohmic contact electrodes, and the bonding area is set as the bonding area 1 for the source electrode corresponding to each electrode.
3', a drain electrode bonding region 14' is provided. That connection is in this case gate metal 1
5 (of course, other metals may be used for connection, but it is advantageous in terms of process to use the gate metal 15). Its plan view is shown in FIG.
In FIG. 3, bonding regions 13' and 1 are provided opposite to the source electrode 13 and the drain electrode 14.
The portion 4' is formed into a concave and convex shape to prevent disconnection when connecting with another metal 15'.
In other words, since there is a level difference in the connection part, there is a certain probability of disconnection, but by making the shape concave and convex in this way, the length of the connection part to the metal 15' is reduced by the increased contact line. This improves the connectivity between the electrodes 13, 14 and bonding regions 13', 14' and the metal 15'. At this time, it is possible to cover the entire surface of the bonding area with the connecting metal 15';
At least the top metal must be a bondable metal.

以下、本発明を実施例によつて詳しく説明す
る。実施例ではヒ化ガリウム結晶を用いたシヨツ
トキ接合型電界効果トランジスタに応用した場合
について説明する。第4図はシヨツトキバリア型
電界効果トランジスタの製造工程断面図である。
第4図aに示すようにヒ化ガリウム基板(半絶縁
性比抵抗108Ωcm)11に能動層12を設け、そ
の上にソース13、ドレイン14のオーム性電極
を設けた。このとき、オーム性接続電極幅は15μ
mであり、他の部分の能動層12は除去し、半絶
縁性ヒ化ガリウム基板11を露出してある。この
露出された基板11上にボンデング用領域をオー
ム性電極13′,14′と分離して同一材料で同時
に形成した。もちろん、ボンデング用領域とオー
ム性電極とは別の材料で、又同一材料であつても
別の工程で形成しても良い。この電極材料は
Au・Ge/Ni/Auの連続蒸着で金属を被着し、各
オーム性電極13,14とボンデング領域1
3′,14′のパターンはホトレジスト膜SiO2膜
16を介した剥離法で形成した。その後、Au・
Ge/Ni/AuをH2雰囲気中で400℃5分間の熱処
理を行ない、オーム性電極は形成した。このとき
ボンデング領域は基板12と合金化されるが、オ
ーム性電極とならない。その後、シヨツトキ接合
金属であるMo17と、ボンデング用金具Au18
を全面に被着し、ホトレジスト膜19AZ1350Jを
6000Å塗布し、第4図bのようにホトレジスト膜
を残した。その後、ホトレジスト膜19をマスク
としてイオンミリングでAu18を除去し、Au1
9をマスクとしてOF4ガスのプラズマMo18を
エツチングする。その後、ホトレジスト膜19も
除去し、第4図cのようにする。第4図cのよう
にオーム性電極13,14と、ボンデング領域1
3′,14′とはMo/Au17′,18′によつて接
続された。その結果、ボンデング作業で従来、15
%程度の発生率で特性不良チツプが発生したが、
本発明でほとんど特性不良チツプ(ワイヤボンデ
ング組立による)は発生しなかつた。また、ゲー
ト・ドレイン間の容量は同一パターンで0.005pF
改善され、利得が10GHzで1dBの改善が見られ
た。これらはボンデング領域を分離したことによ
つて、ワイヤボンデング作業時に能動層に傷をつ
けることがないなどのためである。また、能動層
を最小寸法にしたため、浮遊容量が減少したもの
と考えられる。
Hereinafter, the present invention will be explained in detail with reference to Examples. In the example, a case will be described in which the present invention is applied to a Schottky junction field effect transistor using a gallium arsenide crystal. FIG. 4 is a cross-sectional view of the manufacturing process of a shotgun barrier type field effect transistor.
As shown in FIG. 4a, an active layer 12 was provided on a gallium arsenide substrate (semi-insulating resistivity 10 8 Ωcm) 11, and ohmic electrodes of a source 13 and a drain 14 were provided thereon. At this time, the ohmic connection electrode width is 15μ
m, and other parts of the active layer 12 are removed to expose the semi-insulating gallium arsenide substrate 11. On this exposed substrate 11, a bonding region and ohmic electrodes 13' and 14' were formed separately and simultaneously using the same material. Of course, the bonding region and the ohmic electrode may be made of different materials, or may be formed in different steps even if they are made of the same material. This electrode material
Metal is deposited by continuous vapor deposition of Au/Ge/Ni/Au, and each ohmic electrode 13, 14 and bonding area 1
Patterns 3' and 14' were formed by a peeling method using a photoresist film SiO 2 film 16. After that, Au・
The ohmic electrode was formed by heat treating Ge/Ni/Au at 400°C for 5 minutes in an H 2 atmosphere. At this time, the bonding region is alloyed with the substrate 12, but does not become an ohmic electrode. After that, we applied Mo17, which is a shot-bonding metal, and Au18, which is a bonding metal fitting.
was applied to the entire surface, and a photoresist film 19AZ1350J was applied.
6000 Å was applied, leaving a photoresist film as shown in Figure 4b. After that, Au18 is removed by ion milling using the photoresist film 19 as a mask, and Au18 is removed by ion milling using the photoresist film 19 as a mask.
Using 9 as a mask, OF 4 gas plasma Mo 18 is etched. Thereafter, the photoresist film 19 is also removed to form a structure as shown in FIG. 4c. As shown in FIG. 4c, the ohmic electrodes 13 and 14 and the bonding area 1
3' and 14' were connected by Mo/Au 17' and 18'. As a result, in bonding operations, conventionally 15
Chips with defective characteristics occurred at an incidence of about %, but
In the present invention, almost no chips with defective characteristics (due to wire bonding assembly) were generated. Also, the capacitance between gate and drain is 0.005pF with the same pattern.
The gain was improved by 1dB at 10GHz. This is because, by separating the bonding regions, the active layer will not be damaged during wire bonding work. It is also believed that stray capacitance was reduced because the active layer was made to the minimum size.

また、上記実施例と同じ方法を用い、ボンデン
グ領域を全面に接続金属を被着するだけでなく、
ボンデング領域の凸部分だけとオーム性電極全面
とを接続した結果、実施例と同じ効果を得た。
In addition, using the same method as in the above embodiment, not only the connection metal is applied to the entire surface of the bonding area, but also
As a result of connecting only the convex portion of the bonding region to the entire surface of the ohmic electrode, the same effect as in the example was obtained.

さらに、特願昭50−105897号で述べた様に、ゲ
ート電極に関してもボンデングパツド部を分離す
ることにより、上述した効果をゲート電極に対し
ても得ることができ、又歩留の向上をはかること
ができる。
Furthermore, as stated in Japanese Patent Application No. 50-105897, by separating the bonding pad portion for the gate electrode, the above-mentioned effects can also be obtained for the gate electrode, and the yield can be improved. I can do it.

第5図にその一例を示す。15はゲート電極
(例えばMo/Au)、21はゲート電極引出し部
(Mo/Au)、20はボンデングパツト部(例えば
Au・Ge/Ni/Au)である。
An example is shown in FIG. 15 is a gate electrode (for example, Mo/Au), 21 is a gate electrode extension part (Mo/Au), and 20 is a bonding pad part (for example,
Au・Ge/Ni/Au).

以上の実施例において、オーミツク電極として
Au・Ge/Ni/Auを用いたが、Au・Ge合金のみ
でも良く、又In・Ag,Au・Zn,Sn・Ag,In・
Ge・Ag,Sn・Ge・Ag等のその他の金属が使用
し得る。又シヨツトキー電極としても、他に
Cr/Mo/Au,Al,Ti/Mo/u等も使用し得
る。
In the above embodiments, as an ohmic electrode
Although Au・Ge/Ni/Au was used, it is also possible to use only Au・Ge alloy, or In・Ag, Au・Zn, Sn・Ag, In・
Other metals such as Ge/Ag, Sn/Ge/Ag can be used. It can also be used as a shot key electrode.
Cr/Mo/Au, Al, Ti/Mo/u, etc. may also be used.

以上説明したごとく、本発明のオーム性電極の
構造は素子特性向上に有効なものである。本発明
は半導体材料としてSi、他の化合物半導体にも応
用でき、特にMOS型トランジスタに応用でき
る。オーム性電極とボンデング領域を接続する金
属はオーム性接触用以外のものであれば特に限定
されるものでない。また、外部引出導体はボンデ
ングワイヤに限らず、フリツプチツプボンデング
可能な金属の盛り上げや、ビームリード電極とす
ることは本発明の思想を逸脱するものでないこと
はいうまでもない。
As explained above, the structure of the ohmic electrode of the present invention is effective for improving device characteristics. The present invention can be applied to Si and other compound semiconductors as semiconductor materials, and is particularly applicable to MOS type transistors. The metal connecting the ohmic electrode and the bonding region is not particularly limited as long as it is not for ohmic contact. Furthermore, it goes without saying that the external lead-out conductor is not limited to a bonding wire, but may be a raised metal that can be flip-chip bonded or a beam lead electrode without departing from the spirit of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のオーム性電極の断面構造、第2
図は本発明のオーム性電極の断面構造、第3図は
本発明の平面電極構造、第4図は本発明のオーム
性電極の電極製作工程図、第5図は本発明の他の
実施例を示す図である。図において、 11…基板結晶、12…能動層、13…オーム
性電極又はソースオーム性電極、13′…ソース
電極のボンデング領域、14…ドレインオーム性
電極、14′…ドレイン電極のボンデング領域、
15…ゲート電極、15′…オーム性電極とボン
デング領域とを接続する金属、16…SiO2膜、
17…Mo金属、18…Au金属、17′,18′…
オーム性電極とボンデング領域とを接続する金属
(Mo/Au)、19…ホトレジスト膜である。
Figure 1 shows the cross-sectional structure of a conventional ohmic electrode, and Figure 2 shows the cross-sectional structure of a conventional ohmic electrode.
The figure shows a cross-sectional structure of an ohmic electrode of the present invention, FIG. 3 shows a planar electrode structure of the present invention, FIG. 4 shows an electrode manufacturing process diagram of an ohmic electrode of the present invention, and FIG. 5 shows another embodiment of the present invention. FIG. In the figure, 11... substrate crystal, 12... active layer, 13... ohmic electrode or source ohmic electrode, 13'... source electrode bonding region, 14... drain ohmic electrode, 14'... drain electrode bonding region,
15... Gate electrode, 15'... Metal connecting the ohmic electrode and the bonding region, 16... SiO 2 film,
17...Mo metal, 18...Au metal, 17', 18'...
Metal (Mo/Au), 19... photoresist film connecting the ohmic electrode and the bonding region.

Claims (1)

【特許請求の範囲】 1 所定の半導体基体上に能動層と、該能動層に
接する電極用導体層と、該能動層および電極用導
体層と離れて位置する外部引出し導体取付部用導
体層とを形成し、該電極用導体層と外部引出し導
体取付部用導体層を第3の導体層で導通せしめた
構造を有する半導体装置であつて、前記電極用導
体層と外部引出し導体取付部用導体層の対向せし
めた平面形状は凸部又は凹部のうちの少なくとも
一者を有する形状なることを特徴とする半導体装
置。 2 特許請求の範囲第1項記載の半導体装置にお
いて、前記第3の導体層は複数層より成ることを
特徴とする半導体装置。 3 特許請求の範囲第1項又は第2項記載の半導
体装置において、前記外部引出し導体取付部用導
体層と前記半導体基板とはその界面で少なくとも
合金化反応を呈して構成されていることを特徴と
する半導体装置。
[Scope of Claims] 1. An active layer on a predetermined semiconductor substrate, an electrode conductor layer in contact with the active layer, and a conductor layer for an external lead-out conductor attachment part located apart from the active layer and the electrode conductor layer. A semiconductor device having a structure in which the electrode conductor layer and the external lead conductor attachment part conductor layer are electrically connected by a third conductor layer, wherein the electrode conductor layer and the external lead conductor attachment part conductor layer are electrically connected to each other by a third conductor layer. A semiconductor device characterized in that the planar shape of the opposing layers has at least one of a convex portion and a concave portion. 2. The semiconductor device according to claim 1, wherein the third conductor layer is composed of a plurality of layers. 3. The semiconductor device according to claim 1 or 2, wherein the conductor layer for the external drawer conductor attachment portion and the semiconductor substrate exhibit at least an alloying reaction at the interface thereof. semiconductor device.
JP9605376A 1975-09-03 1976-08-13 Semiconductor d evice Granted JPS5322362A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9605376A JPS5322362A (en) 1976-08-13 1976-08-13 Semiconductor d evice
NL7609676A NL7609676A (en) 1975-09-03 1976-08-31 CONNECTION CONNECTION FOR A SEMICONDUCTOR DEVICE.
DE2639373A DE2639373B2 (en) 1975-09-03 1976-09-01 Connection pad for a semiconductor component
GB36641/76A GB1509160A (en) 1975-09-03 1976-09-03 Bonding pad for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9605376A JPS5322362A (en) 1976-08-13 1976-08-13 Semiconductor d evice

Publications (2)

Publication Number Publication Date
JPS5322362A JPS5322362A (en) 1978-03-01
JPS6128228B2 true JPS6128228B2 (en) 1986-06-28

Family

ID=14154704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9605376A Granted JPS5322362A (en) 1975-09-03 1976-08-13 Semiconductor d evice

Country Status (1)

Country Link
JP (1) JPS5322362A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55147746U (en) * 1979-04-10 1980-10-23

Also Published As

Publication number Publication date
JPS5322362A (en) 1978-03-01

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