JPH0436655U - - Google Patents
Info
- Publication number
- JPH0436655U JPH0436655U JP7841990U JP7841990U JPH0436655U JP H0436655 U JPH0436655 U JP H0436655U JP 7841990 U JP7841990 U JP 7841990U JP 7841990 U JP7841990 U JP 7841990U JP H0436655 U JPH0436655 U JP H0436655U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- peripheral circuit
- signal
- cycle
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 7
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Information Transfer Systems (AREA)
Description
第１図はこの考案の第１の実施例に係るマイク
ロコンピユータシステムの構成を示すブロツク図
、第２図は第１図中の一部の具体的な構成を示す
ブロツク図、第３図は第１図中のＣＰＵの動作を
示すフローチヤート、第４図はＬＣＤコントロー
ラに対するライトサイクル時の第１図の動作を示
すタイムチヤート、第５図はＬＣＤコントローラ
に対するリードサイクル時の第１図の動作を示す
タイムチヤートである。第６図は従来のマイクロ
コンピユータシステムの構成を示すブロツク図、
第７図は第６図のＣＰＵの動作を示すフローチヤ
ートである。
主な符号の説明、１０……ＣＰＵ、１２……Ｌ
ＣＤコントローラ、１１２……アドレスデコーダ
、１２０……ウエイト回路、１４０……データバ
ツフア回路、１５０……イネーブル信号作成回路
。
FIG. 1 is a block diagram showing the configuration of a microcomputer system according to the first embodiment of this invention, FIG. 2 is a block diagram showing a specific configuration of a part of FIG. 1, and FIG. 1 is a flowchart showing the operation of the CPU in FIG. 1, FIG. 4 is a time chart showing the operation of FIG. 1 during a write cycle to the LCD controller, and FIG. 5 is a flow chart showing the operation of FIG. 1 during a read cycle to the LCD controller. This is a time chart. Figure 6 is a block diagram showing the configuration of a conventional microcomputer system.
FIG. 7 is a flowchart showing the operation of the CPU shown in FIG. Explanation of main symbols, 10...CPU, 12...L
CD controller, 112...address decoder, 120...wait circuit, 140...data buffer circuit, 150...enable signal generation circuit.
Claims (1)
サイクルを基本サイクルとするＣＰＵ用の周辺回
路との間に介装したインターフエース回路におい
て、 ＣＰＵ側から周辺回路選択アドレスを入力する
と周辺回路選択信号を出力するアドレスデコーダ
と、 アドレスデコーダから周辺回路選択信号が出力
されたとき、所定の一定期間ウエイト信号を発生
してＣＰＵにウエイトを掛けさせるウエイト回路
と、 アドレスデコーダから周辺回路選択信号が出力
されたとき、リードサイクル時はＣＰＵがリード
ストローブ信号出力中の所定の一定期間、ライト
サイクル時はＣＰＵがライトストロープ信号出力
中の所定の一定期間アクテイブとなるイネーブル
信号を作成し、周辺回路に出力するイネーブル信
号作成回路と、 ＣＰＵと周辺回路との間に介装されてデータ授
受タイミングを調整するデータバツフア回路と、 を備え、かつ、ＣＰＵのライトストローブ端子を
周辺回路のリード／ライトストローブ端子と接続
したこと、 を特徴とするインターフエース回路。[Claims for Utility Model Registration] A CPU whose basic cycle is the T cycle, and an E
In an interface circuit interposed between a CPU peripheral circuit whose basic cycle is a cycle, there is an address decoder that outputs a peripheral circuit selection signal when a peripheral circuit selection address is input from the CPU side, and a peripheral circuit selection signal from the address decoder. When a signal is output, a wait circuit generates a wait signal for a predetermined period of time to make the CPU wait, and when a peripheral circuit selection signal is output from the address decoder, the CPU outputs a read strobe signal during a read cycle. an enable signal generation circuit that generates an enable signal that is active for a predetermined period of time during a write cycle and outputs it to the peripheral circuit while the CPU is outputting a write strobe signal; An interface circuit comprising: a data buffer circuit interposed between the circuits and adjusting the data exchange timing; and a write strobe terminal of a CPU is connected to a read/write strobe terminal of a peripheral circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7841990U JPH0436655U (en) | 1990-07-24 | 1990-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7841990U JPH0436655U (en) | 1990-07-24 | 1990-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0436655U true JPH0436655U (en) | 1992-03-27 |
Family
ID=31621675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7841990U Pending JPH0436655U (en) | 1990-07-24 | 1990-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0436655U (en) |
-
1990
- 1990-07-24 JP JP7841990U patent/JPH0436655U/ja active Pending
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