JPS60201437A - Microprocessor - Google Patents

Abstract

PURPOSE:To cope with an error of a microcode in a ROM by connecting a RAM to a microcode transfer bus, in a microprocessor having an internal data bus and the microcode transfer bus. CONSTITUTION:An output (microcode) of a micro-RAM is outputted to a micro- ROM data bus RDB, and a micro-RAM having the same bit length as the microcode and registers of plural sages inputs data being on an internal data bus DB, and outputs the data to the data bus RDB. An instruction is inputted from an external input terminal of a microprocessor from the outside, and when its instruction is executed, the micro-ROM is brought to access, and the microcode is outputted to the bus RDB. If an error exists in its code, the processor causes a mulfunction, but when the error is detected, a correct microcode group corresponding to a group of the microcode containing the error is sent to the bus DB from the external input terminal, and it is inputted to the RAM. In this way, a correct microcode is obtained from the RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a microprocessor using a microROM control method.

(Prior art) Conventionally, in a microprocessor using a micro ROM control system, the contents of the micro R and OM are outputted to the micro ROM data bus by an output control signal, as shown in FIG. As shown in FIG. 1b), the entire microinstruction register was passed through and outputted to the microROM data bus. The micro ROM data bus has the role of transmitting data (micro instructions) output from the micro ROM to an arithmetic control circuit and the like.

In these systems, when erroneous data is output to the micro ROM data bus due to a data error (micro code error) in the micro ROM, it is rarely possible to correct all of the data. Therefore, due to reasons such as errors in the contents of the micro ROM, the micro I
(Even if it was necessary to modify OM data, analysis of the operation related to the microcode was extremely slow and sometimes impossible. Furthermore, as shown in Figure 1(a)
, (b), it is impossible to modify the output of the micro ROM with software.

(Object of the Invention) An object of the present invention is to provide a one-chip microprocessor that prevents malfunctions caused by code errors in a micro ROM.

(Structure of the Invention) The present invention provides a microprocessor having an internal data bus and a microcode transfer bus, in which an input is connected to the internal data bus and an output is connected to the microcode transfer bus. (RAM), and if there is an error in the microcode in the ROM, write the correct microcode to the RAM via the internal data bus and transfer it to the microcode transfer node (RAM).
To obtain a microprocessor, which is characterized in that it outputs data to a computer.

(Embodiment) Next, the configuration and operation of an embodiment of the present invention will be described using FIG. 2.

The present invention is based on a microROM data bus (RDB) that propagates the output (microcode) of a microROM (μROM).
), and an output control unit 1 that outputs the contents of the micro ROM to the micro ROM data node in response to control number 11 C1.
, a micro RAM (μRAM) having the same bit length as the micro code and multiple stages of registers, and a control signal C2.
includes an input control section 2 that inputs data on the micro nAMKMB data bus (DB) in response to the control signal C3, and an output control section 3 that outputs the contents of the micro RAM to the micro ROM data bus in response to the control signal C3. . Micro ROM
The data bus RD8 and the internal data bus are physically and functionally different types of buses; the former is used exclusively for microcode transfer, and the latter is used to transfer data during calculations and data resulting from calculations. It will be done. Therefore, the former is located inside the processor chip and is not connected to external terminals (there is a processor chip), whereas the latter is used to exchange data between external peripheral devices and the processor. Therefore, it has connection points with external terminals).

In FIG. 2, while the data is on the internal data node, the data can be written into the micro RAM by activating the control signal Csk.

Writing data to the micro RAM can also be done by activating the control signal C2 during the execution of a normal command (such as a data transfer command) that uses the internal data bus, or by writing data to the micro RAM. This is also possible by executing a separately prepared instruction for 114@. The contents of the micro RAM thus stored can be output to the micro ROM data bus by means of the control signal C3. Control signal C1 and control signal Cs
k. By inputting from an external terminal or generated by an internal control circuit, arbitrary data can be sent to the micro ROM data bus as a substitute for output from the micro ROM at any time during processor operation over an arbitrary number of steps. can be output to.

This makes it possible to output the correct microcode to the microROM data bus by writing and reading the correct data to the microRAM even if there is an error in the data in the microROM during prototyping, and the processor's internal operations It is possible to obtain the effect that all analysis processing can be carried out reliably.

5- To explain in more detail, when an instruction is input from the outside through the external input terminal of the microprocessor (this instruction is transferred to the instruction decoder etc. through the internal data bus).
, the micro ROMrj is accessed only when it is determined to be necessary in the execution of the instruction, and the micro code is sequentially output to the micro ROM data bus (LDB). Therefore, if an error occurs in the read microcode, the processor will naturally malfunction. Therefore, in this case, if the operating state of the processor is managed and a malfunction is detected, if it is caused by a microcode error 9 (this can be determined relatively easily by managing the operating state), the error e will be included. A correct group of microcodes corresponding to a group of microcodes (generally, one process is controlled by multiple microcodes) is sent from the external input terminal to the internal data bus (DB), and this is sent to the microR.
Since it is configured such that it is once input to AM and then outputted from there to the micro ROM data bus (riiB) as a correct microcode, the processor can be controlled correctly.

In addition, if there is one Misashi9 microcode, the RAM
may be a Lujistor configuration. Further, when inputting a microcode group, if the register is configured as F'IP'0, the microcodes in the input order are outputted to the bus. If random access is required, it can be accessed using the RAM1 address.

As described above, by incorporating the circuit of the present invention into a microprocessor, even if the circuit is erroneously transferred to a micro ROM, the correct data can be output onto the micro ROM data bus, making it possible to efficiently analyze the operation of the processor. I can do it well.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are block diagrams of a micro ROM and its surroundings in a conventional microprocessor, respectively, and FIG. 2 is a block diagram showing an embodiment of the present invention. μROM...Micro ROM, μRAM...
・・・Micro RAM%RDB・Dan・Micro ROM
Data bus, DB...Internal data bus, TR.
...Microinstruction register, c-c1 to c3...
····Control signal.

Claims (1)

[Claims] A micro) 40M data bus that propagates the output of the micro ROM, an internal data bus having connection points with external terminals, an output end connected to the micro ROM data node, and an input end connected to the internal data node. A microprocessor characterized by an integrated memory means and an integrated memory.