JPS602086A - Rotary phase controller of dc motor - Google Patents

Abstract

PURPOSE:To obtain a rotary phase controller which has stable operation and good reliability by all digitizing the generations of a reference signal, a comparison signal, phase comparison and speed comparison. CONSTITUTION:A counter 7 receives as a set input a reference phase signal from a frequency divider 6, counts the output pulse of a reference oscillator 5, and a latch 8 latches the output of the counter 7 by the output timing of a monostable multivibrator 4. Then, the counter 9 inputs as an input signal the output of the latch 8 by the output timing of the multivibrator 4, and counts the output pulse of the oscillator 5. A latch 10 latches the output of the counter 9 by the timing of the output synchronized with the output of a rotary detector 2 from the multivibrator 3. A D/A converter 11 converted the output of the latch 10 to the analog value, and then supplies it through a motor drive amplifier 12 to a motor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Fields Rotational phase control devices for DC motors that require highly accurate rotational phase control and equipment used such as VTRs.

(b) Prior Art In a device that uses a frequency generator to detect the rotational speed of a DC motor, the speed of the motor is controlled by its discrimination output, and the output of the frequency generator is used when the motor is rotating at a constant speed. A configuration is adopted in which the phase is compared with the output of a reference oscillator that generates substantially the same constant frequency output, and the phase of the motor is controlled using the output. Furthermore, since each circuit is composed of analog circuits, it is susceptible to back fluctuations in ambient temperature or power supply voltage, and is affected by disturbance noise, resulting in a lack of operational reliability and stability. There is.

e> Purpose of the Invention The entire device is digitalized to be unaffected by fluctuations in ambient temperature and power supply voltage, with no drift in the operating point or loop gain, and to improve 8/N by being less susceptible to the effects of external noise. and measure the reliability and stability of operation. Furthermore, it is possible to integrate the device into an IC or use a microprocessor.

2) Configuration of the Invention: A first latch whose data storage timing signal is a constant delayed output of a rotation detector which is connected to a controlled DC motor and whose output is a first counter that is reset at regular intervals and counts the output of a reference oscillator. , and its output is manually applied to a second counter that counts the output of the reference oscillator using the data store timing signal as a load timing signal. The output of this second counter is input into a second latch using a data store timing signal that precedes the load timing output by a certain period of time, and the output is converted into analog to control the rotational phase of the motor.

←) Embodiments The following description will be made with reference to FIG. 1 showing a block diagram of the main parts of the apparatus of the present invention and FIG. 2 showing an explanatory diagram of operating waveforms. 1st
The figure numbers used in the block diagrams in the figures each refer to the following circuits or devices.

(1): Controlled DC motor, for example, a VTR rotating Rad motor.

(2) A two-rotation detector, which is directly connected to the rotating shaft of the DC motor (1) and generates an output voltage having a frequency proportional to the number of rotations of the motor.

(3): The first multi-by-break (abbreviated as the first multi) is triggered by the output of the rotation detector, and has a metastable period Z1 that is sufficiently short compared to one rotation period of the motor. 7 (4): Second multivibrator (second
a pulse which is triggered by the output of the first multi (3) and is sufficient to function as a data store timing pulse of the first latch (8) and a load timing pulse of the second counter (9), which will be described later. Let the width τ2 be the metastable period.

(5): A reference oscillator, a clock pulse generator that generates a fixed period clock pulse having a much shorter period than the period of the rotation detector (2) during steady rotation of the motor (1). shall be. It may also be composed of a sag routine in a microcomputer program.

(6) A frequency divider by two, consisting of a counter, etc., which divides the output of the reference oscillator (5) into pulses with a period equal to or an integral multiple of the pulse period during steady rotation of the motor (the former in this embodiment). Ru.

(7): A first counter is reset by the output of the divider (6), counts the output of the reference oscillator (mu), and supplies the output to the first latch (8).

(8): First latch means (abbreviated as first latch) uses the output of the second monomulti (4) as a data store timing, and latches the output of the first counter (7) at that timing.

(9): Second counter, said second monomulti (4)
The output of the first latch (8) is used as the load timing.
The output pulses of the reference oscillator (5) are counted by using the output of the reference oscillator (5) as input data.

aO): Second latch means (abbreviated as second launch): The output of the first monomulti (3) is used as data store timing, and the output of the second counter is latched at that timing.

Ql): DA converter, a converter that takes the output of the second lunch (10) as a digital input and converts it into an analog value.

(121: Motor-driven amplifier, the D-A converter α
The output of step 1) is amplified to drive the motor (1).

The operation and details of the apparatus of the present invention will be described below with reference to the operational waveform diagram in FIG.

FIG. 2) shows the clock pulse which is the output of the reference oscillator (5). This clock pulse generator is of a type in which the oscillation frequency of a crystal oscillator can be accurately defined, and the frequency is determined in consideration of the desired accuracy of the control system. In FIG. 2(A), the first counter (3) receives the reference phase signal of the frequency divider (6) as a reset input so that the output of the frequency divider (6) plays the role of the reference phase signal.
5) is counted, producing a time-dependent output schematically shown as a staircase wave as shown in FIG. A first latch (8) that uses the output of the second monomulti (4) as a data store timing signal sequentially latches the output of the first counter (3) according to the timing of this signal, and stores subsequent data. The latch value is held until the arrival of the timing signal, and an output as shown in Fig. 2 is produced. This output is used as a phase control signal, and then the second counter (9
) uses the output of the second monomulti (4) as the load timing, takes in the output of the first latch (8) as an input signal, and also outputs the output pulse of the reference oscillator (5) (Fig. 2 (g)). Go as count input. The output of the second counter (9) is sequentially taken in by the second latch (4) which uses the output of the first monomulti (3) as a data store timing signal at the timing of this signal. The data store timing signal of the second latch (4), which is the output of the first monomulti (3), precedes the timing signal of the second counter (9) (O low), so the data store timing signal of the second latch (10) is , only the highest value of the second count (9) is always latched. FIG. 2 (W) shows the output waveform of the second latch α0). The output of the second latch (io) is the D-A converter 01)
After the signal is converted into analog data, if necessary, the power is amplified via a motor drive amplifier composed of a DC amplifier to drive the motor.

(f) Effects of the invention Since all of the λ phase comparison and speed comparison circuits can be digitalized, they are not affected by fluctuations in ambient temperature or power supply voltage, so operating point drift and gain fluctuations do not occur. Furthermore, it is possible to realize a rotational phase control device that has a high S/N ratio, stable operation, and high reliability because it is not easily affected by disturbance noise.

[Brief explanation of the drawing]

The drawings are all related to the present invention; FIG. 1 is a block diagram of a main part of one embodiment, and FIG. 2 is an explanatory diagram of operating waveforms. (1)...DC motor, (5)...Reference signal oscillator, (7)...First counter, <8
+...First latch, (9)-...Second counter, α0)...Second latch, (3)...
...First monomulti, (4)...Second monomulti, (21...Rotation detector.

Claims (1)

[Claims] (1) A rotation detector that is connected to the controlled DC motor shaft and generates a pulse output with a period inversely proportional to the number of rotations; a reference oscillator that generates short periodic pulses;
a first counter that is synchronized with the output of the oscillator and is reset by a pulse having a frequency near the output frequency of the rotation detector or an integral multiple thereof, and counts the output of the reference oscillator; a first monomulti that is triggered; a second monomulti that is triggered by its output; a first latch that uses the output of the second monomulti as a data store timing signal to latch the output of the first counter; a second counter that counts the output of the reference oscillator using the output of the monomulti as a load timing signal and the output of the first latch as input data;
A second latch that uses the output of the first monomulti as a data store timing signal to latch the output of the second counter, a D-A converter that converts the latch output into analog, and the DC motor using the output of this converter. A rotational phase control device for a DC motor, comprising means for controlling the rotational phase of a DC motor.