JPS6020945Y2 - Multi-chip LSI package - Google Patents
Multi-chip LSI packageInfo
- Publication number
- JPS6020945Y2 JPS6020945Y2 JP13406579U JP13406579U JPS6020945Y2 JP S6020945 Y2 JPS6020945 Y2 JP S6020945Y2 JP 13406579 U JP13406579 U JP 13406579U JP 13406579 U JP13406579 U JP 13406579U JP S6020945 Y2 JPS6020945 Y2 JP S6020945Y2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- electrode
- lsi package
- substrate
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は多数のピン端子を有するマルチチップＬＳＩパ
ッケージに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-chip LSI package having a large number of pin terminals.
従来、第１図に示すように、適当な方法で配線を行なっ
たセラミック基板１１に複数のＩＣチップ１６を実装し
てなるマルチチップＬＳＩパッケージにおいては、外部
に対する信号の入出力のために、基板１１の表面に植え
付けられた多数のピン端子１３が用いられる。Conventionally, as shown in FIG. 1, in a multi-chip LSI package in which a plurality of IC chips 16 are mounted on a ceramic substrate 11 wired using an appropriate method, the substrate is A large number of pin terminals 13 planted on the surface of 11 are used.
ピン端子１３の植え付けは、基板１１に孔をあけ、この
孔にピン端子１３を立てることにより行なわれている。The pin terminals 13 are planted by making holes in the substrate 11 and standing the pin terminals 13 in the holes.
このため、ピンとピンとの間隔寸法、すなわち、ピンピ
ッチ寸法の精度は、基板の孔ピツチ寸法精度に依存する
。Therefore, the accuracy of the distance between the pins, that is, the pin pitch, depends on the accuracy of the hole pitch of the substrate.
セラミック基板のように焼成を必要とする材料を基板と
して用いる場合には、加工の容易さから、生テープまた
は粉末成形の段階で孔あけを行なったあとに焼成するの
で、焼成時のセラミックの焼き縮み誤差により孔ピツチ
寸法に狂いを生じ易い。When a material that requires firing, such as a ceramic substrate, is used as a substrate, for ease of processing, it is fired after drilling holes in the green tape or powder molding stage. Shrinkage errors tend to cause deviations in hole pitch dimensions.
特に、マルチチップＬＳＩパッケージのように基板寸法
が大きくかつ多数の入出力ピンを取り出す場合、全ての
ピンに対して高精度のビンピッチ寸法を得ることは難し
く、プリント板またはコネクタへの実装が困難になると
いう欠点がある。In particular, when the board size is large and a large number of input/output pins are taken out, such as in a multi-chip LSI package, it is difficult to obtain highly accurate bin pitch dimensions for all pins, making mounting on a printed board or connector difficult. It has the disadvantage of becoming.
本考案の目的は上記欠点を除去したマルチチップ６■パ
ツケージを提供することにある。The object of the present invention is to provide a multi-chip 6-inch package that eliminates the above-mentioned drawbacks.
本考案のＬＳＩパッケージは、複数のＩＣチップと、前
記ＩＣチップを実装する実装基板と、電極を介して前記
実装基板上に固定されかつ信号入出力用の複数のピン端
子を有するそれぞれが分離独立した複数の端子部とから
構成されている。The LSI package of the present invention has a plurality of IC chips, a mounting board on which the IC chips are mounted, and a plurality of pin terminals for signal input/output that are fixed to the mounting board via electrodes and are separated and independent. It consists of a plurality of terminal parts.
次に本考案について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.
第２ａ図から第２ｃ図は本考案の一実施例を示す図であ
る。Figures 2a to 2c are diagrams showing an embodiment of the present invention.
第２ａ図は多数のピン端子２３を有する複数の端子部２
２を実装基板２１上に実装した状態を示す斜視図、第２
ｂ図は端子部２２と実装基板２１との接合部の拡大断面
図および第２ｃ図は端子部２２の拡大図である。FIG. 2a shows a plurality of terminal parts 2 having a large number of pin terminals 23.
2 is a perspective view showing a state in which 2 is mounted on a mounting board 21.
FIG. 2c is an enlarged cross-sectional view of the joint between the terminal portion 22 and the mounting board 21, and FIG. 2c is an enlarged view of the terminal portion 22.
第２ｂ図において、端子部２２と実装基板２１とは、端
子部２２に設けられた電極２５と実装基板２１に設けら
れた電極２４とを介して接続されている。In FIG. 2b, the terminal portion 22 and the mounting board 21 are connected via an electrode 25 provided on the terminal portion 22 and an electrode 24 provided on the mounting board 21. In FIG.
また、参照数字２１はＩＣチップを示している。Further, reference numeral 21 indicates an IC chip.
第２ａ図および第２ｂ図で明らかなように、端子部２２
は各々独立しており、端子部電極２５は基板電極２４を
逸脱しない範囲で移動、取付が可能なため基板２１上で
の端子部相互の位置合せが容易である。As shown in FIGS. 2a and 2b, the terminal portion 22
are independent, and the terminal electrodes 25 can be moved and attached within a range that does not deviate from the substrate electrode 24, making it easy to align the terminal portions with each other on the substrate 21.
さらに、ピン端子２３のピッチ寸法精度は端子部２２内
だけで独立して考えることができる。Furthermore, the pitch dimensional accuracy of the pin terminals 23 can be considered independently within the terminal portion 22 only.
この場合、端子部２２の大きさは基板２１に比べて十分
中さいのでピンピッチ寸法精度は十分高い値が得られる
。In this case, since the size of the terminal portion 22 is sufficiently medium compared to the substrate 21, a sufficiently high pin pitch dimensional accuracy can be obtained.
したがって、基板全体としてのピンピッチ寸法精度は端
子部を取り付ける治具の精度さえ高めれば、はぼ端子部
内のピンピッチ寸法精度に近い値が得られ、プリント基
板またはコネクタへの実装が容易となる。Therefore, as long as the accuracy of the pin pitch dimension accuracy of the board as a whole is improved as long as the precision of the jig for attaching the terminal section is improved, a value close to the pin pitch dimension precision within the terminal section can be obtained, and mounting on a printed circuit board or connector is facilitated.
第２ｃ図は端子部２２の拡大図であり、ピン端子２３と
端子部電極２５との接続の一例を示す。FIG. 2c is an enlarged view of the terminal portion 22, and shows an example of the connection between the pin terminal 23 and the terminal electrode 25. FIG.
ピン端子２３と端子部電極２５とは回路パターン２７を
介して電気的に接続されている。The pin terminal 23 and the terminal electrode 25 are electrically connected via a circuit pattern 27.
この例の場合、回路パターン２７と端子部電極２５とは
、セラミックにパターンを印刷、焼成することによって
作られており、また、端子部電極２５にはメッキを施す
ことによって基板２１との接続を容易にしている。In this example, the circuit pattern 27 and the terminal electrode 25 are made by printing a pattern on ceramic and firing it, and the terminal electrode 25 is plated to connect it to the substrate 21. It's easy.
なお、基板への取付は、端子部電極２５と基板電極２４
とをハンダ付または導電性接着材で接着することにより
行なわれる。Note that the terminal part electrode 25 and the board electrode 24 are attached to the board.
This is done by soldering or bonding with a conductive adhesive.
第３図は本考案の他の実施例を示す斜視図である。FIG. 3 is a perspective view showing another embodiment of the present invention.
本実施例では、端子部３２とＩＣチップ３６とが基板３
１の同一面上に実装されており、両者の接続は端子部３
２に予め固着した電極リード３８により行なうようにし
たものである。In this embodiment, the terminal portion 32 and the IC chip 36 are connected to the substrate 3.
1 on the same surface, and the connection between the two is through the terminal section 3.
This is done using an electrode lead 38 that is fixed in advance to the electrode 2.
参照数字３３はピン端子である。Reference numeral 33 is a pin terminal.
なお、本考案は端子部の実装位置には何ら制限されるも
のではない。Note that the present invention is not limited in any way to the mounting position of the terminal portion.
また、端子部の形状および構造さらに基板への固着方法
についても同様である。Further, the same applies to the shape and structure of the terminal portion and the method of fixing it to the substrate.
以上、本考案には、ビンピッチ精度が高いため基板また
はコネクタへの実装を容易にできるという効果がある。As described above, the present invention has the advantage that it can be easily mounted on a board or a connector because the bin pitch accuracy is high.
第１図は従来のＬＳＩパッケージの例を示す斜視図およ
び第２ａ図から第２ｃ図と第３図は本考案の実施例を示
す図である。
図において、１１．２１．３１・・・・・・実装基板、
２２．３２・・・・・・端子部、１３．２３．３３・・
・・・ゼン端子、２４・・・・・・基板電極、２５・・
・・・・端子部電極、１６，２６，３６・・・・・・Ｉ
Ｃチップ、２７・・・・・・回路パターン、３８・・・
・・・電極リード。FIG. 1 is a perspective view showing an example of a conventional LSI package, and FIGS. 2a to 2c and 3 are views showing an embodiment of the present invention. In the figure, 11.21.31... mounting board,
22.32...Terminal section, 13.23.33...
...Zen terminal, 24...Substrate electrode, 25...
...Terminal electrode, 16, 26, 36...I
C chip, 27...Circuit pattern, 38...
...electrode lead.
Claims (1)
板と、電極を介して前記実装基板上に固定されかつ信号
入出力用の複数のピン端子を有するそれぞれが分離独立
した複数の端子部とから構成されたことを特徴とするマ
ルチチップＬＳＩパッケージ。A plurality of IC chips, a mounting board on which the IC chips are mounted, and a plurality of separate terminal portions each having a plurality of pin terminals for signal input/output and fixed on the mounting board via electrodes. A multi-chip LSI package characterized by the following structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13406579U JPS6020945Y2 (en) | 1979-09-28 | 1979-09-28 | Multi-chip LSI package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13406579U JPS6020945Y2 (en) | 1979-09-28 | 1979-09-28 | Multi-chip LSI package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5653366U JPS5653366U (en) | 1981-05-11 |
| JPS6020945Y2 true JPS6020945Y2 (en) | 1985-06-22 |
Family
ID=29365638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13406579U Expired JPS6020945Y2 (en) | 1979-09-28 | 1979-09-28 | Multi-chip LSI package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020945Y2 (en) |
-
1979
- 1979-09-28 JP JP13406579U patent/JPS6020945Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5653366U (en) | 1981-05-11 |
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