JPS6235662A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a large capacitance without deteriorating the performance of a transistor and without complicating the process by making insulation films in the grooves of a trench isolation region thicker than insulation films in the grooves of a capacitor part. CONSTITUTION:Relatively thin insulation films 5 are formed on the internal surfaces of U-shape grooves 4a and 4b and the grooves 4a and 4b are filled with conductive materials 6. The capacitance between these conductive materials 6 and a semiconductor substrate 1 is utilized as a capacitor C1. After insulation films 30 are formed on the internal surfaces of U-shape grooves of isolation regions 20, the U-shape grooves are filled with semiconductors 22. The insulation films 30 in the U-shape grooves of the isolation regions 20 are so formed as to be thicker than the insulation films 5 in the U-shape grooves 4a and 4b. With this constitution, owing to the effect that the thicker the insulation film as a dielectric, the smaller the capacitance of a capacitor, the parasitic capacitance between adjacent elements with the trench isolation region in between is avoided so that the performance of the transistor can be improved and a large capacitance can be obtained at the capacitor part.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is effective when applied to the formation of a capacitor in a semiconductor device.
For example, the present invention relates to techniques useful for forming speed-up capacitors for flip-flop memory cells in bipolar transistors.

[Background Art] For example, an emitter-coupled cell as shown in FIG. 4 is known as a memory cell configuration in a bipolar semiconductor memory.
(Page 94 of ``Memory,'' published on 1996).

This memory cell is connected in parallel with load resistors R1, R2 connected between the collectors of multi-emitter transistors Ql, Q2 constituting a flip-flop and the word line W, and a Schottky barrier with low forward resistance. - By connecting the diodes D 1 t D 2, the read current is increased, making it possible to lower the power consumption ratio and increase the read speed.

In the figure, DL and DL are digit lines through which read and write currents are passed, and IST is a current standby line through which a holding current of a memory cell is passed during normal operation (standby).

By the way, in a semiconductor memory having a flip-flop type memory cell as described above, a Schottky barrier diode D 1 r D constituting the memory cell
A technique has been proposed in which speed-up capacitors C1+C2 are provided in parallel with 2, as shown by broken lines in FIG. 4, to improve the operating margin and the resistance to alpha rays.

In addition, as such a capacitor, the capacitance of a Schottky barrier diode can be actively used, and by increasing the area of the Schottky barrier diode, a large capacitance can be connected in parallel with it. is possible.

However, when using the capacitance of a Schottky barrier diode as a speed-up capacitor, the area of the Schottky barrier diode must be increased in order to increase the capacitance value and improve the operating margin and alpha radiation resistance. Must be. However, on the other hand, this increases the area occupied by the memory cell, making it difficult to achieve high integration, and also makes it impossible to obtain a desired Vf value, that is, forward voltage characteristics.

Therefore, the inventor of the present invention used trench isolation in which a trench is dug in the main surface of a semiconductor substrate for isolation between elements, an insulating film is formed on the wall of the trench, and then a dielectric is filled. We have developed a method to use a so-called trench capacitor structure as a speed-up capacitor.

However, in this method using trenched capacitors, in order to simplify the process, the capacitor is made to have exactly the same structure as the trench isolation region, and in order to increase the capacitance, an insulating film is formed on the walls of the trench. When thinned, a non-negligible amount of capacitance is added between adjacent transistors across the isolation region in the isolation region that separates elements, which reduces transistor performance. be.

On the other hand, if the insulation film in the isolation region and the groove of the capacitor is made thicker in order to reduce the capacitance between such transistors, there is the disadvantage that a sufficiently large capacitance value cannot be obtained in the capacitor part. I understand.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that allows a large capacitance value to be obtained without deteriorating the performance of a transistor and without complicating the process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, trench isolation is used for isolation between elements, and the capacitor has a trenched capacitor structure, and the insulating film in the trench in the trench isolation region is made thicker than the insulating film in the trench in the capacitor part. This prevents parasitic capacitance from forming between adjacent elements across the trench isolation region, thereby improving the performance of the transistor, and also allowing a large capacitance value to be obtained in the capacitor portion. This is to achieve the above purpose.

[Embodiment 1] FIG. 1 shows a first embodiment in which the present invention is applied to an emitter-coupled memory cell in a static bipolar memory.

In this embodiment, the elements of the memory cell shown in FIG. 4 surrounded by a dashed line A, namely, a multi-emitter transistor Q1, a Schottky barrier diode D1 connected to its collector, and a speed-up capacitor C1 and 2 is shown in the load resistance of the opposite transistor connected to the base.

In this embodiment, an N medium-sized buried layer 2 is selectively formed on a semiconductor substrate 1 such as a P-type single crystal silicon substrate, and an N- type buried layer 2 is formed by vapor phase growth on this N+ type buried layer 2. U grooves 4a and 4b are formed to penetrate the epitaxial layer 3.

Then, a relatively thin insulating film 5 such as a silicon oxide film is formed inside these U grooves 4a and 4b by thermal oxidation or the like.
The inside of this insulating film 5 is filled with a conductor 6 such as polysilicon into which impurities are introduced. The capacitance between the conductor 6 and the semiconductor substrate is actively used as a capacitor C1.

A Schottky barrier diode D1 is provided in a part of the N-type epitaxial layer M3 adjacent to the capacitor C1.
N-type semiconductor region 7 is formed by selectively introducing an N-type impurity such as phosphorus, and platinum silicide (PtSi) or palladium/
A low resistance conductor layer 8 such as silicide (Pd2Si) and titanium/tungsten (
The barrier electrode 9 is made of a high melting point metal such as TiW.

Although not particularly limited, the barrier electrode 9 is formed from above the semiconductor region 7 forming the Schottky barrier diode D, and the U grooves 4a and 4b forming the capacitor C1.
It is integrally formed above the U grooves 4a and 4b, and is in contact with the conductor 6 in the U grooves 4a and 4b. Further, on this barrier electrode 9, an aluminum layer 10a serving as a word line W is continuously formed.

Adjacent to the N-type semiconductor region 7, a P-type semiconductor region 11 having a relatively large resistance value is formed on the main surface of the N-type epitaxial layer 3 by introducing P-type impurities.
One end of the aluminum layer 10a, which is the word line, is bonded to one end of the P-type semiconductor region 11 via a contact hole 13a formed in the insulating film 12 on the surface thereof.

Further, the other end of the P-type semiconductor region 11 is a multi-emitter
P-type semiconductor region 1 serving as a base region of transistor Q1
It is joined to 4.

Thereby, the P-type semiconductor region 11 acts as a load resistor R2 connected between the word line W and the base of the transistor Q1 in FIG. 4.

By introducing an N-type impurity onto the P-type semiconductor region 14, an N-type semiconductor region 1 which becomes an emitter region is formed.
5a and 15b are formed, and emitter electrodes made of an aluminum layer are formed on the surfaces thereof through contact holes 13b and 13c.

10c is joined. Moreover, this N-type semiconductor region 1
A base electrode 10d is connected to the surface of the P-type semiconductor region 14 between 5a and 15b via a contact hole 13d.

Furthermore, an N-type semiconductor region 16 is formed adjacent to the P-type semiconductor region 14 on the outside thereof (on the right side in the figure) and serves as a collector pull-up port that reaches the N+-type buried layer 2. From the outside of the collector pull-up port (16) to the outside of the U-grooves 4a and 4b constituting the capacitor C1, there is a U-groove isolation region 20 extending through the N+ type buried layer 2 so as to surround these elements. It is formed.

The N+ type buried layer 2 separated by the U-groove isolation region 2o, the P-type semiconductor region 14, and the pair of N-type semiconductor regions 15a and 15b.

A multi-emitter transistor Q1 is configured.

Moreover, the transistor Q separated by the U-groove isolation region 20
In the epitaxial layer 3 on the N+ type buried layer 2 as the collector region of the Schottky barrier diode D1
By forming the N-type semiconductor region 7 constituting the
The cathode terminal of the Schottky barrier diode D1 is connected to the collector of the transistor Q1 via the N+ type buried layer 2. ' Note that the U-groove isolation region 20 has the same structure as the capacitor C1, that is, the epitaxial layer 3 and the N
A U that penetrates the + type buried layer 2 and reaches the semiconductor substrate 1.
It is formed by digging a trench, forming an insulating film 30 inside it, and then filling it with a semiconductor 22 such as polysilicon.

In this case, the U groove of the isolation region 20 is the U groove of the capacitor C1.
6, which can be formed simultaneously with the grooves 4a and 4b,
In this embodiment, the insulating film 30 in the U-groove of the isolation region 20 is formed to be thicker than the insulating film 5 in the U-grooves 4a and 4b forming the capacitor.

Furthermore, in the above case, if the U groove of the U groove isolation region 20 and the U grooves 4a and 4b of the capacitor C1 are to be formed at the same time, the U grooves 4a and 4b will penetrate through the N+ type buried layer 2. It even reaches the substrate 1.

Therefore, the capacitance Cs between the polysilicon (6) in the U grooves 4a and 4b and the substrate 1 is
It will be connected to 0a. This disadvantageously increases the load on the word line.

Moreover, in semiconductor devices to which the conventional U-groove isolation method has been applied,
After digging the U-groove, ion implantation of P-type impurities is performed to form a P+ layer in the lower part of the U-groove isolation region 20 as shown in FIG.
Forming a channel stopper layer 23 of the mold is then performed. Therefore, if such a process is directly applied to the present invention.

A P+ type diffusion layer is also formed under the U grooves 4a and 4b in the portion that will become the capacitor C1, increasing the capacitance with the substrate 1 and further increasing the load on the word line.

Therefore, in this embodiment, an N+ type semiconductor region 17 is formed under the U grooves 4a and 4b so as to be coupled to the N+ type buried layer 2 immediately above the U grooves 4a and 4b.

FIGS. 2A to 2D show an example of the structure of the isolation region 20 and the capacitor portion in the order of manufacturing steps.

In this embodiment, first, N-type impurities are selectively introduced onto the main surface of a semiconductor substrate 1 such as a P-type wheel crystal silicon substrate to form an N+ type buried layer 2, and then the N+ type buried layer 2 is formed. An N-type epitaxial layer 3 is formed on layer 2 by vapor phase growth. Then, a silicon oxide film 25 and a silicon nitride film 26 are formed on the surface, and using these as a mask, the main surface of the semiconductor substrate is etched by reactive ion etching or the like to form a U-shaped film that penetrates the N+ type buried layer 2. Grooves 4a and 4c are formed. After forming an oxide film inside these U grooves 4a and 40 by thermal oxidation (pre-oxidation).

After ion implantation of P-type impurities and annealing are performed to form P+ type semiconductor regions 23 for channel stoppers at the bottoms of the U-grooves 4a and 4c, thermal oxidation is performed to form the U-grooves 4.
A silicon oxide film 41 having a thickness of about 4000λ is formed on the inner walls of portions a and 4c, resulting in the state shown in FIG. 2(A).

Next, by photo-etching, as shown in FIG. 2(B), the silicon nitride film 26 around the U-groove 4a, the silicon oxide film 25 below it, and the silicon oxide film 4 on the inner wall of the U-groove 4a are removed.
After selectively removing 1.

By diffusing N-type impurities into the exposed semiconductor substrate surface, U
An N+ type semiconductor region 17 is formed around trench 4a. This diffusion of the N-type impurity can be performed simultaneously with the formation of the N+-type semiconductor 16 which will serve as the collector pull-up port of the transistor shown in FIG.

After the state shown in FIG. 2(B), the silicon nitride film 26 on the surface is first removed, and then thermal oxidation is performed to form an oxide film 42 of about 100 Å on the inner wall of the U-groove 4a. Then, C
U groove 4a is formed by VD method or the like.

After a silicon nitride film 43 of about 150 Å is formed over the entire surface from the inside of 4c to the substrate surface, the surface is oxidized to form an oxide film 44. Next, 40
After forming a polysilicon layer of approximately 00A, this polysilicon layer is selectively removed by photoetching, leaving the polysilicon layer 45 only in and around the U groove a, resulting in the state shown in FIG. 2(C). becomes.

At this time, the U-groove 4a is made not to be completely filled with the polysilicon layer 45. Furthermore, an impurity such as phosphorus is introduced into this polysilicon layer 45 to lower its resistance.

Thereafter, the oxide film 44 on the surface is removed using the polysilicon layer 45 as a mask, and then a silicon nitride film 46 of approximately 400 Å is formed over the entire surface. The reason why the oxide film 44 is removed before forming the silicon nitride film 46 is to simplify the structure of the insulating film on the substrate surface and facilitate the formation of the contact 6 that will be performed later, so this step is omitted. It is also possible.

After forming the silicon nitride film 46, polysilicon containing no impurities is deposited thickly (approximately 2 μm) and then etched back to planarize the U-grooves 4a and 46.
The polysilicon 47 is left in the area c, thereby completely filling the U grooves 4a and 4c. Thereafter, the surface of the polysilicon 47 is oxidized to form an oxide film 48 of about 400 OA, and then a silicon nitride film 49 of about 100 OA is formed over the entire surface, resulting in the state shown in FIG. 2(D).

Through the steps up to this point, the structure of the U-groove isolation region 20 and the capacitor is completed, and the barrier voltage Vi9 shown in FIG. 1 is brought into contact with the first polysilicon layer 45 in the U-groove a. By this, the polysilicon layer 45 and the U groove 4
The capacitance between a and the surrounding N+ type semiconductor region 17 can be used as a speed-up capacitor C1.

At this time, the polysilicon layer 45 and the N medium semiconductor region 17
The insulation film 42, 4.3.44 between the
Since the capacitance value is about 100%, a considerably large capacitance value can be obtained.

On the other hand, in the U-groove isolation region 20 shown in FIG.
Since the current is 0 A or more and the polysilicon 47 does not contain impurities, almost no parasitic capacitance is generated.

Note that after the state shown in FIG. 2 (CD), the base region, emitter region, etc. of the transistor are formed according to a general bipolar integrated circuit process.

FIGS. 3(A) to 3(D) show other embodiments of the above-mentioned U-groove isolation region and grooved capacitor.

In the process of this embodiment, the steps up to the formation of the final thick oxide film 41 shown in FIG. 2(A) in the above process are the same. Therefore, in this embodiment, the U grooves 4a, 4c
The silicon nitride film 26 is removed while the oxide film 51 is formed by pre-oxidation before the thick oxide film is formed, that is, without forming the thick oxide film 41, and the photoresist film 52 is removed.
By diffusing N type impurities using the mask as a mask and forming an N+ type semiconductor region 17 around the U groove 4a, the state shown in FIG. 3A is obtained.

Thereafter, the photoresist film 52 and the oxide film 51 are removed and thermal oxidation is performed to re-grow the oxide film 51 on the inner walls and surfaces of the U grooves 4a, 4c by about 100 Å. Then, C
U groove 4a is formed by VD method or the like.

After a silicon nitride film 43 of about 150 Å is formed over the entire surface from the inside of 4c to the substrate surface, the surface is oxidized to form an oxide film 44. Next, 40
After forming a polysilicon layer 45 of approximately 00A, the upper part of the U groove 4a is covered with a photoresist film 53, as shown in FIG. 3(B).
The state will be as follows.

Thereafter, using this as a mask, etching is performed to selectively remove the polysilicon layer 45, leaving the polysilicon layer 45 only in and around the U groove a.

At this time, the U-groove 4a is made not to be completely filled with the polysilicon layer 45. Furthermore, an impurity such as phosphorus is introduced into this polysilicon layer 45 to lower its resistance.

Thereafter, the oxide film 44 on the surface is removed using the polysilicon layer 45 as a mask, and then a silicon nitride film 46 of approximately 400 Å is formed over the entire surface. The reason why the oxide film 44 is removed before forming the silicon nitride film 46 is to simplify the structure of the insulating film on the surface of the substrate and facilitate the formation of the contact hole 1, which will be performed later. It is also possible to omit it.

After forming the silicon nitride film 46, a thick silicon oxide film 54 of about 4000 Å is formed on the entire surface by the CVD method, and a polysilicon film 54 containing no impurities is further formed on the silicon oxide film 54, which is about 4000A thick.
7 is deposited thickly (approximately 2 μm) and then etched back to remove the silicon oxide film 54 from the polysilicon on the surface of the substrate.
4, the silicon oxide film 54 and polysilicon 47 are left in 4c, thereby forming the U groove 4a.

Completely fills out 4c. After that, polysilicon 47
The surface is oxidized to form an oxide film 48 of about 400 OA, resulting in the state shown in FIG. 3(C).

As a result, in the capacitor part, the U-groove a is filled with polysilicon through a thin insulating film, and in the U-groove isolation region 20, the U-groove is filled with polysilicon through a thick insulating film. is obtained.

Note that the structure and professional chopsticks in which the insulating film in the U-groove is different between the capacitor portion and the U-groove isolation region portion are not limited to those shown in FIGS. 2 and 3.

[Effect] Using trench isolation structure for isolation between elements,
In addition, the capacitor has a trenched capacitor structure, and the insulating film on the wall of the trench in the trench isolation region is formed to be thicker than the insulating film on the wall of the trench in the capacitor area. The thicker the insulating film, the smaller the capacitance, which prevents parasitic capacitance from forming between adjacent elements across the trench isolation region, thereby improving transistor performance and reducing the capacitance of the capacitor. This has the effect that a large capacitance value can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the configuration of the memory cell is not limited to that of the above embodiment, and may be one in which the Schottky barrier diode is omitted, or a resistor element is actively connected in series with the Schottky barrier diode. It may also be a configuration in which

The conductor layers 10a, 10b, 10c, etc. have a region 11°ISa
, ISb, etc., for example, a first conductor layer made of silicide of a high melting point metal, a second thick layer made of a high melting point metal, and a third thick layer made of aluminum. may be configured.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing another example of cell construction and process when the present invention is applied to an emitter-coupled memory cell in a bipolar memory, and FIG. 4 is an example of the configuration of a memory cell in a conventional bipolar memory. FIG. 1... Semiconductor substrate, 2... N medium-sized buried layer, 3...
...N-type epitaxial layer, 4a, 4b...U
Groove, 5... Insulating film, 6... Conductor (polysilicon containing impurities), 7... N-type semiconductor region, 9...
... Barrier electrode, 10a... Aluminum layer (word line), 11... P-type semiconductor region (load resistance), 1
2... Insulating film, 14... P-type semiconductor region (base region), 15a, 15b... N-type semiconductor region (emitter region), 16... N-type semiconductor region (collector pull-up ), 17... N+ type semiconductor region, 20...
... U-groove isolation region, 21°41-44 ... Insulating film,
22,45.47...Polysilicon, 23...
Channel stopper layer, Ql, C2...multi-emitter, transistor. R1, R2...Load resistance -Di + D2...
Schottky barrier diode, C1, C2...
Speed-up capacitor, W...Word line. IST...Current standby line, DL, DL...
digit line. Figure 2Figure 2

Claims (1)

[Scope of Claims] 1. A semiconductor in which semiconductor elements formed on the main surface of a semiconductor substrate are separated by a trench isolation region formed by digging a trench in the main surface of the semiconductor substrate and filling it with semiconductor. An integrated circuit device, wherein an insulating film is formed inside a groove formed on the main surface of the semiconductor substrate, a capacitor having a structure filled with a semiconductor is formed inside this insulating film, and this capacitor A semiconductor integrated circuit device, wherein the insulating film on the inner wall of the trench in the portion is formed thinner than the insulating film on the inner wall of the trench in the trench isolation region. 2. Claim 1, wherein the grooved capacitor is adapted to be used as a speed-up capacitor connected in parallel with a Schottky barrier diode in an emitter-coupled memory cell.
The semiconductor integrated circuit device described in .