JPS6197960A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology and technology that is effective when applied to the formation of capacitors in semiconductor devices, such as speed-up for flip-flop type memory cells in bipolar transistors. - Concerning techniques that are effective in forming capacitors.

[Background Art] As a structure of a memory cell in a bipolar semiconductor memory, for example, the structure shown in FIG. 1 is known ("Memory", p. 94, published by the Institute of Electronics and Communication Engineers).

This memory cell includes multi-emitter transistors Q1. A Schottky barrier diode D with low forward resistance is connected in parallel with the load resistor R1tR2 connected between the collector of Q2 and the word line W.
By connecting 1 + D 2, the read current is increased, making it possible to reduce power consumption and increase the read speed.

In FIG. 1, DL and DL are digit lines through which read and write currents are passed, and IST is a current standby line through which a holding current of a memory cell is passed during normal operation (standby).

-By the way, in a semiconductor memory having a flip-flop type memory cell as described above, the Schottky barrier diode D 1 + D constituting the memory cell
A technique has been proposed in which speed-up capacitors C1 and C2 are provided in parallel with 2, as shown by broken lines in FIG. 3, to improve the operating margin and the strength against alpha rays.

In addition, as such a capacitor, the capacitance of a Schottky barrier diode can be actively used, and by increasing the area of the Schottky barrier diode, a large capacitance can be connected in parallel with it. is possible.

However, when using the capacitance of a Schottky barrier diode as a speed-up capacitor, the area of the Schottky barrier diode must be increased in order to increase the capacitance value and improve the operating margin and alpha radiation resistance. Not necessarily. On the other hand, however, this disadvantageously increases the area occupied by the memory cell, making it difficult to achieve high integration, and making it impossible to obtain a desired Vf value, that is, forward voltage characteristics.

OBJECTS OF THE INVENTION An object of the invention is to improve the degree of integration of semiconductor memories consisting of flip-flop memory cells with speed-up capacitors.

Another object of the present invention is to provide a memory cell structure that can improve the operating margin and resistance to alpha rays without increasing the cell area in a semiconductor memory consisting of a flip-flop type memory cell having a speed-up capacitor. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, in a semiconductor memory consisting of a flip-flop type memory cell, a groove is dug in the main surface of the semiconductor substrate, an insulating film is formed on the inner surface of the groove, and then the groove is filled with a conductor and used as a speed-up capacitor. This makes it possible to achieve large capacity in a small area and to optimize the forward voltage characteristics of the Schottky barrier diode, improving the degree of integration of semiconductor memory and improving memory cell operation. This achieves the above-mentioned objective of improving margin and alpha ray resistance.

The present invention will be described in detail below using the drawings.

[Embodiment 1] FIG. 1 shows a first embodiment in which the present invention is applied to a memory cell having a flip-flop configuration in a static bipolar memory.

The memory cell of this embodiment has a configuration in which the capacitors C1t-C2 shown by broken lines are formed as independent elements in the flip-flop type memory cell shown in FIG. In FIG. 1, the elements surrounded by a dashed line A, namely a multi-emitter transistor Q1 and a Schottky barrier diode D connected to its collector, are shown.
1 and the speed-up capacitor C1 and the opposite transistor load resistor R2 connected to the pace.

In this embodiment, U is formed so as to penetrate through an N+ buried layer M2 selectively formed on a P type silicon semiconductor substrate 1 and an N~ type epitaxial layer 3 formed by vapor phase growth on this N+ buried layer 2. Grooves 4a and 4b are formed.

Then, a relatively thin insulating film 5 such as a silicon oxide film is formed inside these U grooves 4a and 4b by thermal oxidation or the like.
The inside of this insulating film 5 is filled with a conductor 6 such as polysilicon into which impurities are introduced. The capacitance between the conductor 6 and the semiconductor substrate is actively used as a capacitor C1.

A Schottky barrier diode D1 is provided in a part of the N-type epitaxial layer 3 adjacent to the capacitor C1.
N-type semiconductor region 7 is formed by selectively introducing an N-type impurity such as phosphorus, and platinum silicide (PtSi) or palladium/
A low resistance conductor layer 8 such as silicide (Pdst) and titanium/tungsten (Ti
The barrier electrode 9 is made of a high melting point metal such as w).

Although not particularly limited, the barrier electrode 9 extends from above the semiconductor region 7 forming the Schottky barrier diode D1 into the U grooves 4a and 4b forming the capacitor C1.
It is integrally formed above the U grooves 4a and 4b, and is in contact with the conductor 6 in the U grooves 4a and 4b. Further, on this barrier electrode 9, an aluminum layer 10a serving as a word line W is continuously formed.

Adjacent to the N-type semiconductor region 7, a P-type semiconductor region 11 having a relatively large resistance value is formed on the main surface of the N-type epitaxial layer 3 by introducing P-type impurities.
One end of the aluminum layer 10a, which is the word line, is bonded to one end of the P-type semiconductor region 11 via a contact hole 13a formed in the insulating film 12 on the surface thereof.

Further, the other end of the P-type semiconductor region 11 is a multi-emitter
P-type semiconductor region 1 serving as a base region of transistor Q1
It is joined to 4.

Thereby, the P-type semiconductor region 11 acts as a load resistor R2 connected between the word line W and the base of the transistor Q1 in FIG.

By introducing an N-type impurity onto the P-type semiconductor region 14, an N-type semiconductor region 1 which becomes an emitter region is formed.
5a and 15b are formed, and an emitter electrode 10b made of an aluminum layer is formed on the surface thereof through contact holes 13b and 13c.

10c is joined. Moreover, this N-type semiconductor region 1
A base electrode 10d is connected to the surface of the P-type semiconductor region 14 between 5a and 15b via a contact hole 13d.

Furthermore, adjacent to the P-type semiconductor region 14.

On the outside (on the right side in the figure), an N-type semiconductor region 16 is formed that reaches the N+ buried layer 2 and serves as a collector pull-up port. A U-groove isolation region 20 penetrating the N+ buried layer 2 is formed from the outside of the collector pull-up port (16) to the outside of the U-grooves 4a and 4b constituting the capacitor C1 so as to surround these elements. has been done.

N0 buried layer 2 separated by this U-groove isolation region 20
A multi-emitter transistor Q1 is constituted by the P-type semiconductor region 14 and the pair of N-type semiconductor regions 15a and 15b.

Moreover, the transistor Q separated by the U-groove isolation region 20
By forming the N-type semiconductor region 7 constituting the Schottky barrier diode D1 in the epitaxial layer 3 on the N+ buried layer 2 serving as the collector region of the Schottky barrier diode D, the cathode terminal of the Schottky barrier diode D is formed. is N
+ is connected to the collector of the transistor Q1 via the buried layer 2.

Note that the U-groove isolation region 20 has the same structure as the capacitor C1, that is, the epitaxial layer 3 and the N
+It is formed by digging a U-groove that penetrates the buried layer 2 and reaching the semiconductor substrate 1, forming an insulating film 21 inside it, and then filling it with a semiconductor 22 such as polysilicon.

In this case, the U groove of the isolation region 20 is the U groove of the capacitor C1.
The grooves 4a and 4b can be formed simultaneously. Similarly, the insulating films 5 and 21 inside the V-groove of the isolation region 20 and the capacitor C1 can be formed at the same time, and the polysilicon films 5 and 22 to be filled inside them can also be deposited at the same time. .

However, structurally, the insulating film 5 of the capacitor C1 portion
The thinner the material, the larger the capacity.

Further, since it is preferable that the U-groove isolation region 20 has no parasitic capacitance, the insulating film 21 within the one isolation region 20 is preferably thicker. Therefore, it is better to form the insulating films 5 and 21 separately. Also, for the same reason, polysilicon as a conductor containing impurities is placed in the U grooves 4a and 4b of the capacitor C1, and dielectric containing no impurities is placed in the U groove of the one isolation region 20. It is preferable to fill it with polysilicon. The U-trench isolation region 20 may be replaced with a relatively thick field oxide film using known iso-placing techniques.

According to the memory cell structure of the above embodiment, the width and mutual spacing of the U-grooves 4a and 4b, which form the capacitor C1, can each be reduced to approximately 1 μm using current processing technology.

Therefore, compared to the conventional method (Fig. 3) in which the area of the Schottky barrier diode DITD2 was increased in order to obtain good operating margins and alpha-ray resistance, this embodiment has a smaller occupied area. Capacitance of the same size can be achieved with a capacitor consisting of a U-groove. As a result, the original Schottky barrier diode D 1 r D 2 can be made one-tenth or less smaller than the conventional one. As a result, the area occupied by the entire memory cell can be reduced by approximately 20 to 30%.

Furthermore, according to this embodiment, the size of the U-groove forming region, which determines the capacitance of the capacitor C1, and the size of the Schottky barrier diode D1 can be designed separately. - The Vf characteristics of the barrier diode and the capacitance value of the capacitor for improving α-ray resistance can be independently optimized. Therefore, it is possible to simultaneously improve the operating margin and the resistance to alpha rays of the flip-flop type memory cell of the high-speed bipolar memory.

[Example 2] In the above example, since the U groove of the U groove isolation region 20 and the U grooves 4a and 4b of the capacitor C1 are formed at the same time, the U grooves 4a and 4b are formed with the N+ buried layer 2. It penetrates and reaches the substrate 1. Therefore, the capacitance Cs between the polysilicon (6) in the U grooves 4a, 4b and the substrate 1 is connected to the aluminum layer 10a which is a word line. This disadvantageously increases the load on the word line.

Moreover, in semiconductor devices to which the conventional U-groove separation method has been applied,
After digging the U-groove, P-type impurity ions are implanted to form a P+ layer in the lower part of the U-groove isolation region 20 as shown in FIG.
Forming a channel stopper layer 23 of the mold is then performed. Therefore, if such a process is directly applied to the present invention, the U-groove 4a of the portion that becomes the capacitor C1,
A P+ type diffusion layer is also formed in the lower part of 4b, and the capacitance with the substrate 1 becomes larger than that of the structure shown in FIG. 1, and the load on the word line becomes even heavier.

Therefore, in the second embodiment, at the bottom of the U grooves 4a and 4b,
An N+ type semiconductor region 17 is formed to be coupled to the N+ buried layer 2 immediately above it.

Therefore, in the embodiment shown in FIG. 1, the polysilicon (6) in the U grooves 4a, 4b and the N-
In this embodiment, in addition to the above capacitance, polysilicon (6) is connected between the word line and the collector of transistor Q1, with the only effective capacitance being the capacitance between The capacitance between the capacitor C1 and the N+ type semiconductor region 17 is also effectively connected, increasing the capacitance of the capacitor C1.

Moreover, according to this embodiment, the capacitance Cs that existed between the polysilicon layer and the substrate l in the embodiment of FIG. 1 is eliminated. Therefore, there is an advantage that the load on the word line is reduced and the rise of the word line to the selection level becomes faster.

Note that the N+ type semiconductor region 17 is a U groove 4a.

4b and before or after the ion implantation for forming the channel stopper layer 23, N-type impurities can be implanted into the bottoms of the U grooves 4a and 4b by ion implantation or thermal diffusion.

In the above embodiment, the U groove in the part that becomes the capacitor C1 is 2
Although the U-groove formed in strips is shown, it is also possible to form three or four or more U-grooves. In addition, Schottky barrier diodes D1+D2 and multi-emitter transistors Q1. The structures of Q2 and load resistors R□ and R2 are not limited to the above embodiments.

For example, the load resistors R1 and R2 may be polysilicon resistors instead of diffused resistors. Also, the transistor Q1.
Q2 may have a structure in which a relatively shallow U-groove isolation region or oxide film isolation region is formed between the base (14) and the collector pull-up port (16), penetrating only the N-type epitaxial layer N3.

In that case, a U groove 4a for configuring the capacitor C1,
4b may be formed at the same depth as the U-groove of the shallow U-groove isolation region.

[Effects (1) In semiconductor memory consisting of flip-flop memory cells, a trench is dug in the main surface of the semiconductor substrate, an insulating film is formed inside the trench, and then a conductor is filled in to speed up the process. Since it is used as a capacitor, a large capacity can be obtained in a small area, which has the effect of reducing the area occupied by the memory cell and improving the degree of integration of the semiconductor memory.

(2) In a semiconductor memory consisting of flip-flop memory cells, a groove is dug in the main surface of the semiconductor substrate, an insulating film is formed inside the groove, and then a conductor is filled, which is used as a speed-up capacitor. As a result, the forward voltage characteristics of the speed-up capacitor and Schottky barrier diode can be independently optimized, which improves the operating margin and α resistance of the memory cell.
It has the effect of simultaneously improving the line strength.6 Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and the gist thereof is as follows. It goes without saying that various changes can be made without departing from the above. For example, the configuration of a flip-flop memory cell is not limited to that of the above embodiment, and may be one in which the Schottky barrier diode is omitted, or a resistor element is actively connected in series with the Schottky barrier diode. It may also be a configuration in which they are connected.

Further, the structure of the U-groove isolation region and the speed-up capacitor and the process thereof are not limited to the above-mentioned embodiment, and various modifications can be easily considered.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of the cross-sectional structure of the main part of a cell when the present invention is applied to a flip-flop type memory cell in a bipolar memory, and FIG. 2 is a cross-sectional view showing a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a memory cell in a conventional bipolar memory. Ql, Q:z...multi-emitter transistor,
R1, R2... Load resistance, D 1 y D 2...
...Schottky barrier diode, C1, C2...
...Speed-up capacitor, W...Word line. IST...Current standby line, DL, DL...
Digit line, 1...Semiconductor substrate, 2...N+
Buried layer 3...N-type epitaxial layer, 4a. 4b... U groove, 5... Insulating film, 6... Conductor (polysilicon containing impurities), 7... N-type semiconductor region, 9... Barrier electrode, 10a ...Aluminum layer (word line), 11...P-type semiconductor region (
load resistance) -, 12...insulating film, 14...P-type semiconductor region (base region) -15a, 15b...N
type semiconductor region (emitter region), 16... N type semiconductor region (collector pull-up port), 17... N medium semiconductor region, 20... U groove isolation region, 21... Insulating film , 22... Dielectric or conductor (polysilicon), 23... Channel stopper layer.

Claims (1)

[Claims] 1. A semiconductor memory device including a memory array consisting of memory cells having a flip-flop configuration in which a capacitor is connected in parallel with a load resistance element, wherein the capacitor is formed on the main surface of a semiconductor substrate. 1. A semiconductor memory device characterized in that an insulating film is formed inside a groove, and a conductor is filled inside the insulating film. 2. In the case where the groove is formed so as to penetrate the epitaxial layer formed on the main surface of the semiconductor substrate and the buried layer thereunder to reach the semiconductor substrate, there is a conductive layer below the groove that is different from the semiconductor substrate. 2. The semiconductor memory device according to claim 1, wherein a semiconductor layer of a type is formed so that the bottom of the groove is surrounded by the semiconductor layer. 3. In a semiconductor memory device in which semiconductor elements formed on the main surface of a semiconductor substrate are separated by a trench isolation region formed by digging a trench in the main surface of the semiconductor substrate and filling it with semiconductor, a flip-flop The capacitor in the type memory cell has a structure in which an insulating film is formed inside a groove formed on the main surface of a semiconductor substrate, and a conductor is filled inside the insulating film. Claim 1
3. The semiconductor memory device according to item 1 or 2.