JPS60238964A - Controller of data holding circuit - Google Patents

Abstract

PURPOSE:To obtain the controller of the data holding circuit which uses a microcomputer having a small number of input/output ports by using a time- division output signal for supplying a digit signal of a display body even as the output signal for data hold control of the data holding circuit. CONSTITUTION:A scanning signal output from an output port A supplies the digit signal of the display body 2 through a driving circuit 12 to supply a data holding command to data holding circuits 3-6. When data is held at the fall of a scanning signal, data of output ports D at falls of pulses of respective A-1- A-4 are held by the data holding circuits. Data (0, 1, 0, 1) of the output port D are held at the fall timing of A-1. Similarly, data (1, 0, 1, 0) of the output port D are held at the fall timing of A-2, data (0, 0, 0, 1) of the output port D are held at the fall timing of A-3, and data (1, 1, 0, 0) of the output port D are held at the fall timing of A-4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data holding circuit control device using a microcomputer.

Conventional configuration and its problems In recent years, external data holding circuits have been frequently used around microcomputers to hold data output and input. Furthermore, for the purpose of expanding input/output, a method is used in which one time-division signal is used to read input and control devices such as large-digit numeric displays.

A conventional data holding circuit control device will be explained below.

FIG. 1 is a block diagram of a conventional data holding circuit control device. 1 is a 4-bit 1-chip microcomputer with internal RAM, ROM, and CPU.

It has a built-in input/output board. 2 is a 4-digit display consisting of 7-segment display elements. 3,4°6.6 is 4
This is a bit data holding circuit. 7.8.9.10 is a drive circuit for an external device controlled by the 4-bit data held in the data holding circuit. 11 and 12 are display drive circuits. A-D are output ports, one outputs scan signals, B [7 segment data output, c
Vf, clock pulse signal output %D id giving timing for data retention of data retention circuits 3, 4, 5.6
They are configured to each output 4-bit data output.

3.- The operation of the conventional data holding circuit control device configured as described above will be explained below. First, the display control section will be explained. A scan signal specifying the digit of the display body 2 is output from the human output boat in one time division, and is inputted to the one display body 2 via the drive circuit 12. The display element specified by the 7-segment data of the B output port that is input at the timing when this pulse is at a high level emits light. Next, the data holding circuit side leg will be explained. The output of the C output port provides data retention timing to the data retention circuits 3, 4, and 5.6, and is a clock pulse output that becomes high level, 6, or low level as required. data holding circuit 3,
4, 5, and 6 are the rising % or falling % of the pulse from the C output port.

It holds 4 bits of data from the D output port and controls the drive circuits 7, 8, 9 and 10 of external devices, respectively.

FIG. 2 shows clock pulse outputs C-1, C-2, and C-3 from the C output port that provide data retention timing to the data retention circuits 3, 4, and 5.6.

Data output D-1゜D- from C3-4 and D output boat
2 is an example of a timing chart showing the relationship between D-2, D-3, and D-4. When data is held at the falling edge of the clock pulse, the data (o, o, o, 1) of the D output boat at the falling edge of the clock pulse output C-1 is held in the data holding circuit 3. Similarly, clock pulse output c-
Data at each falling edge of 2, C-3°c-4 (
1,1゜0.0), (1,0,1,O), (0,1,0
1) is held in the data holding circuits 4, 5.6.

However, in the above configuration, since a large number of output ports are required, there are problems such as a shortage of output ports or one circuit becoming complicated.

Purpose of invention The present invention solves the above-mentioned conventional problems.

The time division output signal that gives the digit signal of the display body is shared with the output signal for data retention control of the data retention circuit. The purpose is to provide

Composition of the invention The present invention reads input in a time-sharing manner.

A time division output signal that controls an external device such as a multi-digit display in a time division manner, a data output signal to an external data holding circuit,
It is equipped with a microcomputer that generates a retention control output signal that gives the retention timing to the external data retention circuit, and by sharing the time division output signal and the retention control output signal, fewer input/output ports can be used. It is designed to be configurable.

DESCRIPTION OF EMBODIMENTS FIG. 3 is a block diagram of a control device for a data holding circuit using a microcomputer, which is an embodiment of the present invention.

In FIG. 3, %1 is a 4-bit 1-chip microcontroller, internal VCRAM, ROM, and OPυ.

It has a built-in input/output board. 2 is 7 segments 6・＼
゛It is a 4-digit display body consisting of display elements. 3,4°5.6
is a %4-bit data holding circuit. 7゜8.9.1
0 is a drive circuit for an external device (eg, motor 1 display, plunger) controlled by 4-bit data held by the data holding circuit. A, B, and D are output ports of the microcomputer. The human output port 1 is a scan signal output that controls the display 2 in a time-division manner, and at the same time is a clock pulse output that gives data retention timing to the data retention circuits 3, 4, 5.6. The B output port outputs data signals for 7-segment display.

The D output ports are configured to respectively output data signal outputs held by the data holding circuit.

The operation of the microcomputer-based data holding circuit control device of this embodiment configured as described above will be described below.

First, the scan signal output from the single-person output boat passes through the drive circuit 12 and provides a digit signal for the display 2.

And data holding circuits 3, 4, 5.6 have data holding circuits 7I\
−Give a holding command.

Figure 4 shows the scan signal output A-1 from the single output port.
, A-2, A-3, A-4 and data outputs D-1, D-2, D-3, D-4 of the D output port. When data is held at the falling edge of the scan signal, the data at the D output port at the falling edge of each pulse of A-1, A-2, A-3, and Mu-4 is stored in the data holding circuit. is retained. At the falling timing of person-1, the data of the D output boat (0,1°0.1
) is retained. Similarly, at the falling timing of person-2, the data (1,0°1,o) of the U and D output ports becomes %A.
At the timing of the fall of -3.

The data (o, o, o, 1) of the D output port becomes the data (1, o, o, 1) of the D output port at the falling timing of mu-4.
1, o, O) are respectively retained.

In this way, the output of the held data holding circuit controls the drive circuits 7, 8, 9.1o of the external device shown in FIG.

As described above, according to this embodiment, by sharing the time-divided scan signal output that provides the display digit signal and the clock pulse output that provides the data retention timing to the external data retention circuit, input/output can be reduced. It is very advantageous to be able to configure the side legs of an external data retention circuit on the boat.

Effects of the Invention The present invention is configured with fewer input/output ports by sharing an output signal that sterilizes an external device in a time-sharing manner and a control output signal that provides timing for data retention in an external data retention circuit. It is possible to provide a control device for an external data holding circuit using a microcomputer.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional control device for a data holding circuit, Fig. 2 is a timing waveform diagram for explaining the operation of the conventional example, and Fig. 3 is a control device for a data holding circuit which is an embodiment of the present invention. FIG. 4 is a timing waveform diagram for explaining the operation of the present invention. 1...Microcomputer, 2...
Display body. 9・＼− 3, 4, 5, 6... Data holding circuit, 7, 8,
9゜1o... External device drive circuit, 11.12
...Display drive circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 @ 3 Figure 4 ρ-4 ], 1

Claims (1)

[Claims] A time-division output signal for reading input in a time-division manner and controlling an external device such as a multi-digit display in a time-division manner, and a data output signal to an external data holding circuit. A data holding circuit comprising: a microcomputer that generates a holding control output signal that gives holding timing to an external data holding circuit; and the data holding circuit shares the time division output signal and the holding control output signal. Control device.