JPH0351928A - System reset circuit - Google Patents

Abstract

PURPOSE:To surely reset an input/output port when the working of a CPU is interrupted by using a retriggerable single shot circuit. CONSTITUTION:A CPU 21 outputs a phi clock in its active state, and the output time of a high level signal, i.e., the desired output is decided for a retriggerable single shot circuit 33 based on a time constant secured between a capacitor 34 and a resistance 35. In this case, the output time is set longer than the cycle of the phi clock. This phi clock is stopped if the working of the CPU 21 is interrupted and therefore the transmission of the desired output is stopped from the circuit 33. Then an input/output port 24 is reset. As a result, the port 24 is surely reset when the CPU 21 is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention relates to a reset circuit for a system provided with a central processing unit and an input/output port that becomes inactive upon reset.

[Prior Art] As a conventional system of this type, the one shown in FIG. 3 is known. This is the CPU (
(central processing unit) 1, ROM (read-only memory) 2, which stores program data for this CPU to control various parts, RAM (random access memory), which has memory for temporarily storing processing data, etc. ) 3, I/O (input/output) ports 4 that become inactive upon reset are provided, and are connected to each other via bus lines 5.

A solenoid drive circuit 7 for driving the solenoid 6 and a motor drive circuit 9 for driving the motor 8 are connected to the I/O port 4, respectively.

A reset ICII is connected to the DC power supply 10, and an output terminal of the reset ICII is connected to a reset terminal of the CPUI and a reset terminal of the I/O port.

In this circuit, when the power supply 1o is turned on, the reset IC1
1 outputs a low level signal from the output terminal to hold the CPUI and I/O port 4 in a reset state until the power supply voltage rises above a predetermined level, and when the power supply voltage rises above a predetermined level, the output terminal outputs a low level signal. The reset state of the CPU I and I/O port 4 is released by outputting a high-level signal from the I/O port 4.

However, in this circuit, if the CPU 1 goes out of control during operation, the I/O port 4 will not be reset and will remain in the active state, so there is a risk that the solenoid 6 and the motor 8 will operate abnormally.

For this reason, the one shown in FIG. 4 is known as an improved version of this.

This is an I/O port when enabled.
The I/O port 4' that outputs the /O enable signal is used to control each drive circuit 7.9 with both the drive signal and the I/O enable signal, and when the CPU goes out of control, the I/O
The enable state of the port 4' is released, the output of the I/O enable signal is stopped, and the operations of the solenoid 6 and motor 8 are forcibly stopped to ensure safety.

[Problems to be Solved by the Invention] In the past, it was possible to deal with a runaway CPU, but it was not possible to deal with an accident in which the CPU stopped midway. That is, if the operation stops, for example, when the I/O port 4' is activating each of the drive circuits 7 and 9, there is a risk that the solenoid 6 and the motor 8 will continue to operate without being stopped.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a system reset circuit that can reliably reset input/output ports when a central processing unit stops during operation.

[Means for Solving the Problems] The present invention provides a system including a central processing unit and an input/output port that becomes inactive by reset and outputs an enable signal when in an enabled state.
It is set to transmit a desired output for a period longer than the clock cycle triggered by a clock output from the central processing unit when the central processing unit is operating, and the next clock is input during the transmission period of the desired output. A retriggerable single shot circuit that is retriggered is provided, and the input/output port is reset when the desired output from the single shot circuit is stopped.

[Function] In the present invention having such a configuration, when the central processing unit is operating, the retriggerable single shot circuit continues to be retriggered by the clock output from the central processing unit to obtain the desired output from the shot circuit. continues to send out. This puts the input/output port into an enabled state.

If the central processing unit stops mid-operation, the clock output from the central processing unit is stopped, so the desired output from the retrigger-pull single-shot circuit is stopped and the output port is reset. is,
Becomes inactive.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

As shown in Fig. 1, the CPU (
A central processing unit) 21, a ROM (read-only memory) 22 in which program data for controlling various parts of the CPU 21 is stored, and a RAM (random access memory) in which a memory for temporarily storing processing data, etc.
Memory) 23, I/I that becomes inactive due to reset
O (human output) ports 24 are provided and connected via bus lines 25, respectively.

A solenoid drive circuit 27 that drives a solenoid 26 and a motor drive circuit 29 that drives a motor 28 are connected to the I/O port 24, respectively. Also, the above I/
An I/O enable signal is supplied from the O port 24 to each of the drive circuits 27 and 29.

A reset IC 31 is connected to the DC power supply 30, and the output terminal of the reset IC 31 is connected to the reset terminal of the CPU 21 and one input terminal of a two-power negative logic OR circuit 32.

The CPU 21 outputs a φ clock during operation, and supplies this φ clock to the retriggerable single shot circuit 33. The retriggerable single shot circuit 33 has a time constant of a capacitor 34 and a resistor 35 to determine the output time of a high level signal, which is a desired output, and this output time is longer than the period of the φ clock, for example, It is set to about twice the period. Therefore, the retriggerable single shot circuit 33 continues to be retriggered as long as the φ clock is continuously inputted, and continues to output the noise level signal.

The output terminal of the retriggerable single shot circuit 33 is connected to the other human input terminal of the OR circuit 32. The output terminal of the OR circuit 32 is connected to the reset terminal of the I/O port 24.

In this embodiment with such a configuration, (a) in FIG.
As shown in FIG. 2, when the DC power supply 30 is turned on, the output level of the reset lc 31 is at a low level as shown in FIG. 2(b) until its output voltage reaches a predetermined level.

Thus, the CPU 21 and the I/O port 24 are put into a reset state.

Thereafter, when the output voltage from the DC power supply 30 reaches a predetermined level, the output level of the reset IC 31 is inverted to high level, the CPU 21 and the I/O port 24 are released from the reset state, and the I/O port 24 is enabled. .

When the CPU 21 is released from the reset state, it enters the operating state and begins to output the φ clock as shown in FIG. 2(c).

However, retriggerable single
The shot circuit 33 is repeatedly triggered to (r
), a high level signal is output continuously.

In this state, the I/O port 24 is controlled by the CPU 21, and as shown in FIG. 26 are individually driven.

If an accident occurs in which the operation of the CPU 21 stops during such control, the output of the φ clock stops as shown in FIG. 2(e). At this time, if the output from the I/O port 24 to the solenoid drive circuit 27 is just stopped, the solenoid 26 will stop operating. Also, from the I/O port 24 to the motor drive circuit 2
Assuming that the output to the motor 9 continues, the motor 28 will continue to operate thereafter.

However, as the output of the φ clock is stopped, the output of the high level signal from the retriggerable single shot circuit 33 is eventually stopped as shown in FIG. 2(f), and the output becomes low level. In this way, a low level reset signal is input to the reset terminal of the I/O port 24, and the I/O port 24 is reset. Therefore, the I/O port 24 becomes inactive, and as shown in FIG. 2(d), the output to the motor drive circuit 29 is stopped and the operation of the motor 28 is forcibly stopped.

In this way, safety is ensured when the CPU 21 stops operating.

Further, when the CPU 21 goes out of control, the enable state of the I/O port 24 is released, so the output of the I/O enable signal is stopped. Therefore, at this time, even if the solenoid drive circuit 27 and the two motor drive circuits are in operation, their operations are immediately stopped.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a system reset circuit that can reliably reset input/output ports when the central processing unit stops during operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation timing of each part in the same embodiment, and FIGS. 3 and 4 are block diagrams showing a conventional example. 21...CPU (central processing unit), 22...RO
M (read-only memory), 24...I/O
Port (human output port), 33... Retriggerable single shot circuit.

Claims (1)

[Claims] becomes inactive due to central processing unit and reset;
In a system provided with an input/output port that outputs an enable signal when the central processing unit is in an enabled state, the central processing unit is triggered by a clock output from the central processing unit and outputs a desired output for a period longer than the clock cycle. A retriggerable single shot circuit is provided that is set to transmit and is retriggered when the next clock is input during the transmission period of the desired output, and when the desired output from this single shot circuit is stopped. A system reset circuit that resets the input/output port.