JPS6024013A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short circuit in P-N junction even when a metal is selectively formed over there, by selectively depositing Si in a contact hole. CONSTITUTION:SiO2 is deposited on a P type Si wafer, and an aperture hole is provided therein. Ions are implanted from the surface of the wafer 1 to form a region 3. Then amorphous Si containing As 4 and 4' are evaporated over there, and is subsequently heat treated. The amorphous layer with implantation of As ion is thereby subjected to epitaxial glowth from the substrate side, and the Si deposited in the aperture hole is also subjected to epitaxial glowth, so as to become single crystal, while the Si 4' is left amorphous. In the next, step, after the Si 4' is removed, W 5 is glowth selectively in the aperture hole by a pressure reducing CVD for running tungsten hexafluoride. In this case, since Si single crystal exists in the aperture hole, the W glown to the SiO2-Si interface does not reach the P-N junction, so that no short circuit occurs in the junction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a highly integrated microscopic device, particularly a device structure that produces good results when applied to the formation of electrodes.

[Prior art and its problems] Semiconductor devices, such as integrated circuit devices, have become increasingly highly integrated and fast in recent years, but factors that hinder this are conversion differences due to mask alignment and signal delays due to wiring resistance. There is. As an effective means to improve this, there is a metal selective formation technique.

However, metal films produced using the selective growth method are only thin, and the resistance value is several times higher than that of metal films produced using sputter deposition methods, which is an obstacle to practical application. Also, when filling contact holes for shallow pn junctions, Si
)・Surface 8i is consumed due to the substitution reaction with metal halogenide, and metal grows under SiOz, forming a shallow pn
There were problems such as the joints sagging.

[Object of the Invention] The present invention has been made in view of the above circumstances, and eliminates the problems and drawbacks of the conventional selective metal formation method by selectively depositing St in the contact hole. The present invention provides a method for manufacturing an element structure.

[Summary of the Invention] In the present invention, amorphous Si is first formed in the contact hole.
(or Ge) is deposited and annealed to make the amorphous Si only in the contact hole grow by solid-phase epitaxial growth.The surrounding amorphous Si on the 8402 is kept in an amorphous state, and then the amorphous Si on the 5iOz layer is chemically etched. After removing Si, polymetals are selectively grown on the openings by metal halide gas phase reaction.

[Effects of the Invention] The first effect of the present invention is that 87-
Even if metal grows at the 3iQ2 interface, it remains at the solid-phase growth St-side wall 5iOz interface within the opening, so that no p-n junction occurs due to the metal. Furthermore, a second effect is that since the solid phase epitaxial growth temperature used is low, the depth of the pn junction will not become deeper even if such an additional process is newly added.

Furthermore, as a third effect, as the opening becomes shallower, when the second metal is taken out from the metal and wired over 8A02, there is less chance of disconnection due to the difference in level between the second metal and the opening. I can do it.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

First, p-type SI Ueno 1 K 5000X S rice 02
2 was formed, a hole of 4 x 4 μrlL2 was formed in this, and a hole of 3 x 10
/Cr/l As ions are implanted to form region 3 (
Figure 1).

Wash the surface with a hydrofluoric acid solution diluted to about 1/20, dry it, and put it directly into a high vacuum evaporation device to remove As from 7XIO20.
Amohy7 containing /cI/8i 4 and 4' is deposited at 350 OX (FIG. 2). Alternatively, instead of this surface treatment, sputter etching is performed in a vapor deposition apparatus and then vapor deposition is performed. After vapor deposition, the wafer was partially held at 350° C. in vacuum, taken out, and heat-treated at 600° C. for 2 hours in an electric furnace. As a result, the pAs ion-implanted amorphous layer was epitaxially grown from the substrate side, and the deposit S1 in the opening was also epitaxially grown to become a single crystal, but in this annealing, the deposited Si 4/ on 5i022 was amorphous. This amorphous Si is dissolved with nitric hydrofluoric acid. Opening part 81 is 7001
It only dissolves to a certain extent. This is due to the large difference in etching rate between amorphous 8i and single crystal Si. Next, flow 2 Cc of tungsten hexafluoride, 4 A, 11/minute at a rate of 35
Apply 150% tungsten 5 to the opening by low pressure CVD at 0'O.
0 (Fig. 3).

The bonding depth by this method was 2700X. Since a Si single crystal portion exists in the opening, tungsten grown on the 5iOz-8i interface does not reach the pn junction. Therefore, there is no junction short circuit. This process did not change the Si junction depth, but for comparison, the Si deposition in the open hole was
This was done by selective epitaxial growth of H4. in this case,
The bonding depth was 4000K.

Finally, wire A16 and cover PSG7 (Figure 4)
. Since the opening of 8i becomes shallow due to solid phase growth at the opening, disconnection of M does not occur in this part.

Next, the open-hole i9i Ueno was washed as described above, and 250% Ge containing the same <1x 1o"7crit of As was washed as described above.
0X, lXl0''/d 100OX of St containing gold was evaporated and annealed at 600°C, resulting in solid phase growth of Ge and Si deposited on the openings in lhr.Amorphous S-singing Ge on 8102 was removed by etching. Then 6 from above
By selectively growing W at 1500X by vapor phase reaction of tungsten fluoride, and then covering M with wiring and PSG, it is possible to fill a contact hole with a shallow junction and low resistance.

As described above, according to the present invention, the pn junction is shallow due to the low-temperature process, and since there is Si, Ge, or a mixed crystal of these in the opening, the selectively grown metal does not short-circuit the pn junction, and the opening does not short-circuit the pn junction. Since the difference in level is reduced, it is possible to obtain an excellent electrode that does not cause disconnection when wiring with the second metal. - Although tungsten hexafluoride is shown as an example of the metal halide, molybdenum fluoride may also be used. In addition, chlorides of these may also be used. Although the vapor deposition method has been described for depositing silicon, polycrystalline silicon may be deposited and then made amorphous by ion implantation.

[Brief explanation of the drawing]

1 to 4 are process cross-sectional views for explaining one embodiment of the present invention. l...Silicon wafer, 3...Ion implantation region, 5...Tungsten.

Claims (2)

[Claims] (1) Depositing amorphous silicon on a semiconductor substrate formed by exposing an insulating film region and a conductor region containing silicon, or depositing polycrystalline silicon or single crystal silicon on the exposed silicon. A process of depositing polycrystalline silicon on the insulating film and making the deposited silicon amorphous by ion implantation, a process of solid-phase epitaxial growth of only the amorphous silicon on the silicon region by annealing, and a process of removing the amorphous silicon on the insulating film. 1. A method of manufacturing a semiconductor device, comprising the step of selectively forming a metal or metal silicide film in an S- region using a metal chloride. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that Ge is used as part or all of the amorphous semiconductor deposited in the silicon region or by ion implantation after deposition.