JPS604224A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a cross section of an aperture from becoming a reverse trapezoid in the aperture drilling process of a double-layer structure of a PSG layer and a non-doped SiO2 layer by a method wherein a phosphorus glass film is made grow and subjected to a heat-treatment and then a non-doped SiO2 layer is formed on it. CONSTITUTION:A PSG layer is formed and subjected to a heat-treatment. Then a non-doped SiO2 layer is formed on it. For instance, in order to produced an MOS FET, after a PSG layer is formed, the layer is subjected to a heat-treatment in an N2 atmosphere at 1,000 deg.C for 10-20min. With this heat-treatment, a PSG layer 51' which has a reduced etching rate for a fluoric acid system etchant is obtained. The etching rate of this layer is approximately the same as that of a non-doped SiO2 layer 61 which is formed on the PSG layer 51' afterwards. Therefore, by making the non-doped SiO2 layer 61 grown after the heat- treatment of the PSG film 51', etching rate of an upper layer and etching rate of a lower layer are nearly equal so that a cross section of an aperture for a contact window made by the next process has the same shape as that in the case of the non-doped SiO2 layer only.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semi-quadramid element, and more particularly to a method for manufacturing an element in which phosphor glass layers are made equal.

The normal cross-sectional structure of MO8 field effect transistor is
It looks like the picture. That is, a gate oxide film 21 is formed on the Si substrate 11, and a gate electrode 31 (for example, MO or polycrystalline Si) is formed on the gate oxide film 2.
Using this gate electrode 31 as a mask, a skin-through type diffusion layer 41 is formed as a source and drain region on the 8i substrate through the gate oxide film 21 by ion implantation.

In the example shown in the figure, a p-channel MO8FE is created by implanting N-type, for example, Rinkei ions into a p-type substrate.
T is forming. 5i doped with phosphorus after washing
O21 Mo51 (hereinafter referred to as PSG) and a doped (undoped) 5i02 film 61 are sequentially formed by vapor phase growth, etc. This stabilizes the ions in the gate oxide film, and improves the transistor characteristics using the BT process unique to MO8. This is a generally known technique to prevent Jl from fluctuating.Next, S (source)
, J) (drain) and G (gate) regions are opened and a metal such as aluminum 71 is deposited for electrical connection to the outside. The above is a well-known general MO8FIJ
This is a method for manufacturing T.

Here, in order to reduce the number of mask processes as much as possible7 and bring out productivity and cost benefits, the opening of the contact window for electrode connection is made in one P H and one mask process.
Hydrofluoric acid-based wet etching is used to simultaneously open holes in layer 51 and non-doped 5iOz layer 61. But at this time,
Since the lower PSG layer 51 has a higher etching rate than the upper non-doped 8102 layer 61, the cross section of the opening is an inverted trapezoid, as shown in FIG.
The shape of the layer 51 is largely etched in the lateral direction, and the aluminum electrode that will be formed later has a break point, which significantly lowers the Th reliability of the device.

An object of the present invention is to provide a manufacturing method that prevents the opening [0] from becoming an inverted trapezoid in the opening process of a 21i4+4 structure consisting of a PS ( ) layer and a non-doped 5in2 layer.

In the present invention, after forming the PS() layer, it is heat-treated in an inert gas atmosphere, thereby making the film structure of )'S(+) dense. As a result, the etching rate for the non-oxygen etchant of the P2O layer can be made comparable to that of the non-doped 5I02 layer, and the electrode opening JCm can be formed without increasing the number of mask steps.

An embodiment of the present invention will be described below with reference to FIG.

In this example, in an example of the manufacturing method of M (JS J'ET), after forming a P2O layer, this layer f6: 1000°C
By performing heat treatment for 10 to 20 minutes in an N2 atmosphere, a P SO layer 51' whose etching rate with respect to a hydrofluoric acid etchant is reduced from 6000X/min to 3000X/min is obtained. This layer C has approximately the same root IW as the etching rate of the upper non-doped SiO□61 layer formed by the wave. Therefore, PSGlia51
By growing the non-doped 5iOz layer after the heat treatment of ', the etching rates of the upper and lower layers are almost equal, so when contact g is opened in the next process, the cross-sectional shape will be exactly the same as when only the non-doped 8102 layer is used. become. Therefore, no breakage of the aluminum due to the inverted trapezoidal cross-section of the contact portion occurs. Furthermore, since the PSG layer 51' without lateral etching has already been formed when the hole is opened, the electrode cutout can be formed in one mask process.

As described above, the manufacturing method according to the present invention is very effective in improving the reliability of devices.
It can be applied not only to the case of , but also to other methods of manufacturing semiconductor devices.

[Brief explanation of drawings]

Figure 1 is a sectional view of a conventional MOS FET pellet, Figure 2 is a cross-sectional view of a conventional MOS FET pellet.
The figure is a sectional view of N+O8FgT according to one embodiment of the present invention. 11... Semiconductor substrate (P-type Si), 21...
... Gate oxide film, 31 ... Gate electrode, 4
1°・°°°° Source and drain region, 51.51'
...P2O layer, 61...-non-doped 5
iOz layer, 71...aluminum electrode. Agent Patent Attorney Hiji Uchihara

Claims (1)

[Claims] In the manufacturing process of a semiconductor device having a two-layer structure of returned phosphor glass and non-doped 5ra2, the phosphor glass IIK
1. A method for manufacturing a semiconductor device, which comprises growing a semiconductor device, heat-treating the same, and then forming a non-doped layer 5i02 thereon.