JPS60242580A - MOS static type RAM - Google Patents

Abstract

PURPOSE:To obtain a MOS static RAM with high reliability by providing a function which stops selectively the equalizing operation of complementary data lines with a signal from an external terminal and stopping the equalizing operation during a test of operation, etc. CONSTITUTION:A write enable signal WE' supplied from the external terminal is supplied to the gate of a MOSFETQ12. A gate insulating film is used as a field insulating film so as to make the threshold voltage of the Q12 higher than a source voltage VCC, and a MOSFETQ11 is provided as a load between its drain and the source voltage VCC. The drain output of the Q12 is sent as a control signal to an AND gate AND. When the write enable signal WE' goes up to a high level, the Q12 turns on and generates a low-level drain output, and the AND gate is closed to stop equalizing pulses phia. Consequently, a function test is taken on severe operation condition, so the high-reliability MOS static RAM is obtained.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a static RAM (Random Access Memory) composed of MOSFETs (Insulated Gate Field Effect Transistors).
The present invention relates to a technique that is effective for use in a circuit configured with a C'MO3 (complementary MO3) circuit.

[Background technology]

The memory array in MOS static RAM is
The input/output terminals of the static flip-flop circuit constituting the memory cell are connected to a pair of complementary data lines D via a transmission gate MOSFET (ISSCC82).
DIGESTTECHNICAL PAPER3 No. 25
6-257). This complementary data line D is provided with a MOSFET as a load resistance. The conductance characteristic of the MOS FET serving as this load resistance is set to a small value. This is because memory arrays consist of a large number of memory cells in order to increase storage capacity.
The element size is formed small. Then, when the transmission gate 1-MO3FET is turned on and the input/output terminals of the flip-flop circuit are connected, the drive MO which is in the on state constituting the flip-flop circuit
Since the read low level of the complementary data line is determined according to the conductance characteristic ratio of the conductance characteristics of the MO5FET and the transmission gate MO5FET and the conductance characteristic of the load MO3FET, the conductance characteristic of the load MO3FET is inevitably set small. Therefore, in the read operation of memory cells provided for the same complementary data line, when inverted reading is performed, in other words, after reading the storage information of logic "0", the storage information of logic "1" is read. In this case, the previous logic “0” information remains in the complementary data line, so the load MO with the small conductance characteristic
A problem arises in that it takes a relatively long time to change from low level to high level using 3FET.

Therefore, an equalization method using an address clock is used, which detects changes in the address signal and shorts the complementary data lines to equalize the potentials of both complementary data lines (
(Japanese Unexamined Patent Publication No. 152931/1983). However, research by the inventors of the present application has revealed that such an equalized MOS static RAM has a problem in that it becomes difficult to detect defects in element characteristics.

In other words, even if there is a level defect in the stored information due to a defect in the element characteristics, the potentials of the complementary data lines become equal due to the above-mentioned equalization (tJ), so even if there is some level defect, the data can be read out correctly. . However, if the defects in the element characteristics are progressive, or under severe operating conditions such as when the power supply voltage is reduced, read failures due to the device characteristics may occur.

[Purpose of the invention]

The purpose of this invention is to provide a highly reliable MOS static type R
The aim is to provide AM.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a function is provided to selectively stop the equalization operation of the complementary data line using a signal from an external terminal.
This allows the equalization operation to be stopped during operation tests and the like.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM in the figure may be a known CM
O3 (complementary-metal-insulator-semiconductor) integrated circuit (IC)
) technology on a semiconductor substrate such as a silicon single crystal.

Terminals AX+ Ay+ Din, Dout, WE and C
S is its external terminal. Note that the power supply terminal is omitted in the figure.

One specific circuit of the memory cell MC is shown as a representative, and includes memory MO5FETQI, Q2 whose gates and drains are cross-connected to each other, and the MO3FETQ mentioned above.
High resistances R1 and R2 formed of a polysilicon layer for information retention are provided between the I, Q2 (7))' rain and the power supply voltage Vcc. And the above M
O3FETQ1. ．． Q2 common connection point and complementary data line D
Transmission gate MO3FETQ3, 0.4 between O and DO
is provided. Other memory cells MC also have similar circuit configurations. These memory cells are
Arranged in a matrix. The gates of the transmission gates 1-M03FETQ3, Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines WO, Wl, Wn, etc. shown as examples, respectively, and are arranged in the same column. The input/output terminals of the memory cells are connected to a pair of exemplified corresponding complementary data (or pin 1 lines Do,
Connected to Do, DI, DI, etc.

In the above memory cell MC, in order to make it have low Ipl power, the resistor R1 can maintain the gate voltage of MO3FETQ2 above the threshold voltage when the MOS FETQl is turned off. The resistance value is set as high as possible. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 is MO3'FETQ
The MO3FET Q2 is designed to have a current supply capability sufficient to prevent the information charges multiplied by N in the gate capacitance (not shown) from being discharged due to the drain leakage current of the MO3FETQ2.

In the figure, the word line WO is connected to the X address decoder
-Selected by the output signal formed by the NOR gate circuit G1 forming the DCR. This also applies to the other word lines Wl and Wn.

The X-address decoder X-DCR is composed of mutually similar NOR gate circuits G1, G2, 03, etc. These NOR gate circuits Gl.

G2. Input terminals such as c and 3 are provided with an X address buffer
- Internal complementary address signals processed and formed by ADB are applied in a predetermined combination. Although not particularly limited, an internal control signal φ is commonly supplied to the NOR gate circuits 01 to G3 and the like in order to prevent wasteful current consumption during the deep selection state. Due to the high level (logic "1") of this internal control signal φ, all word lines are rendered unselected during the chip non-selection period.

A pair of complementary data lines DO, D in the memory array
o, DI, and DI are transmission gates MO3FETQI for data line selection, respectively.3. G14 and G15. Q
It is connected to the common complementary data lines CD and CD through a column switch circuit composed of 1 and 6. This common complementary data line CD.

An input terminal of a read circuit RA and an output terminal of a write circuit WA are connected to the CD. A read signal is sent to the output terminal 6 (main data output terminal 1) out of the read circuit RA, and a write data signal supplied from the data input terminal Din is applied to the input terminal of the write circuit WA.

MO3FETQ1 that constitutes the above column switch circuit
3. G14 and G15. Selection signals YO and Yl formed by the Y address decoder Y-DCH are supplied to the gates of Ql and 6, respectively.

This Y address decoder Y-DCR has mutually similar NOR gate circuits G4. , G5, etc.

These NOR gate circuits G4. Internal complementary address signals processed and formed by a Y address buffer Y-ADB that receives an external address signal AY (address signal output from an appropriate circuit device not shown) consisting of a plurality of bits are applied to G5 etc. in a predetermined combination. be done.

The control circuit C0NT receives control signals from external terminals WE and C3 and forms the internal control signal φ and the like.

N-channel MO3FE''FQ5 to Q8 are provided as loading means for the pair of complementary data lines DO, Do and DI, DI shown as representative in the memory array.

These MO3FETs Q5 to Q8 are brought into a steady operating state by having their gates and drains connected in common and being supplied with a power supply voltage Vcc. These MO3
The conductance characteristics of the FETs Q5 to Q8 are those of the information storage MO5FETQI' in the memory cell MC.

G2 and transmission gate MO3FE, TQ3. It is set sufficiently small compared to the composite conductance characteristic with Q4. For example, the high level on the complementary data lines Do and DO is 3.
, 5■, the low level is set to about 3■.

In this embodiment m, the following equalization circuit is provided in order to speed up the read operation. That is, address signals AX and AY are supplied to an address signal change detection circuit ΔT'D, where an address signal change detection pulse φq is formed. This detection pulse φq is applied to the MO5FETQ9 . Supplied to the gate of QIO.

As a result, the MO3FETQ9. QIO and the like are turned on, and the above-mentioned no-y level and low level of the complementary address signal remaining from the previous operation cycle are short-circuited to make them the same potential. Thereafter, when a word line is selected and one memory cell MC is selected, the potentials of the complementary data lines Do, Do, DI, Dl, etc. are determined according to the stored information. By doing so, inversion reading of the memory cell MC can be performed at high speed.

In this embodiment, the operation of the address signal change detection circuit ΔTD is selectively stopped by a signal from an external terminal in order to detect with high precision a defect in the characteristics of the elements constituting the memory cell MC. . In this embodiment, although not particularly limited, the write enable signal WE is used as the control signal, and the signal level is set to
When the voltage is higher than the voltage Vcc, for example, 7V, it is detected and the above operation is stopped.

FIG. 2 shows a circuit diagram of an embodiment of the address signal change detection circuit ATD.

The circuit for detecting a change in the address signal is an exclusive OR circuit EX which receives the address signal AXO supplied from an external terminal and its delayed signal formed by the delay circuit DLO.
It is composed of O. This exclusive OR circuit EXO is
When the address signal AXO changes, the delay circuit D L
An address signal change detection pulse having a pulse width corresponding to the delay time of O is formed. Other address signals AXI to AXi
7 is also provided with a circuit similar to the above. These address signal change detection pulses are supplied to an OR gate circuit OR, and from its output terminal the MO3FET
Q9. It is sent out as an equalization pulse φq supplied to QIO and the like.

In this embodiment, an AND gate is connected to the output of the OR gate circuit OR in order to stop sending out the pulse φq when the signal level of the write enable signal WE is set to a higher level than the normal signal level. circuit an
D is provided, and the following circuit is provided to form its control signal.

That is, the write enable signal WE supplied from the external terminal is supplied to the gate of MO3FETQ12.

The threshold voltage of this MO3FIETQI 2 is set to a value higher than the power supply voltage Vcc. Since the threshold voltage is set at such a high level, there are no particular restrictions, but
A MOSFET is used in which a field insulating film is used as a gate insulating film. (7) MO3FET QI 217) Between the drain and the power supply voltage vcc, there is an MO3 as a load.
A FETQII is provided. And the above MO3FET
The drain output of QI 2 is connected to the AND gate circuit AN
D as a control signal. For example, if the write enable signal WE is set to a high novel like 7■, M
O3FETQ'12 is turned on and the drain output is set to low level (logic "0"). This closes the AND gate circuit AND, so that the sending of the pulse φq is stopped. Note that at a normal signal level, MO8F+F and TQ12 are always in the off state, so the gate of the AND gate circuit AND remains open, and the equalization pulse φq is sent out according to the change in the address signal. .

Ia that selectively stops the equalization operation in this way
The ball launch with the function will be explained according to the operation waveform diagram shown in FIG.

When the equalization operation is stopped as described above, for example, the read level from the previous operation remains on the complementary data lines 1) O and DO in FIG. 1, as shown by dotted lines. Assume now that the data line DO is at a high level and the data line Do is at a low level.

Then, the next selected memory cell is MO5FETQI
When an inverted signal is stored, such as when MOS FETQ2 is on and MOS FETQ2 is off, MO3FETQI
The drain potential of MO3FETQ2 is at low level, and the drain potential of MO3FETQ2 is at high level. However, the word line is selected and the transmission gate MO3FETQ3. When Q4 turns on, the drain potential of the MO3FET QI in the on state is raised by the high level of the remaining previous data line DO under the low AC impedance due to its parasitic capacitance, and the remaining previous data line DO is also raised. Due to the low level of DO, the drain potential of MO3FETQ2 in the off state is lowered. This lowers the storage level of the memory cell.

Therefore, if the MO3FET has deteriorated element characteristics,
If QI, Q2, etc. are present, the information stored in the memory cell will be inverted during the above read operation. By stopping the equalization operation in this manner, severe operating conditions can be created, and therefore the accuracy of detecting defective pitches in the functional test can be increased.

〔effect〕

(1) By adding a function to selectively stop the equalization function, the function test can be performed under severe operating conditions, increasing detection accuracy and resulting in highly reliable MOS static RAM) ! E-fJ
You can get the effect of being able to do a lot of things.

(2) Since the write enable signal WE is used to detect its high level and stop the above-mentioned equalizing operation, the above-mentioned high reliability can be achieved with an extremely simple circuit without adding any external terminals. It is possible to obtain the effect that it is possible to obtain the effect of being able to do the following.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. The circuit for stopping the equalization operation described above can take various embodiments. For example, the circuit that makes the write enable signal WE high voltage and detects it is a MOSFE.
The signal level may be lowered by using the threshold voltage of T, etc. L2, and then supplied to a MOS FET or an inverter circuit for level determination. Alternatively, only a bonding pad may be provided and a signal for stopping equalization may be supplied from a probe only during a functional test, or an external terminal may be added.

It also constitutes a static type RAM. Memory cells are P-channel MO3FET and N-channel M, 03F.
A static flip-flop circuit constructed by combining ET may also be used. As described above, the configuration of the memory array and the specific circuit configuration of its peripheral circuits can take various embodiments.

[Application field]

This invention can be widely applied to MOS static RAM.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the address signal change detection circuit, and FIG. 3 is a waveform diagram showing an example of the read operation. It is. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, MC...memory cell, WA...write circuit, RA...read circuit,
C0NT...Control circuit, ATD...Address signal change detection circuit, EXO~EX1...Exclusive OR circuit, D
LO~DLi...delay circuit, OR...OR gate circuit,
AND・Figure 1

Claims (1)

[Claims] 1. An address signal change detection circuit that detects a change in an address signal, and an equalization MO3FET that shorts a pair of complementary data lines constituting a memory array by the detection output pulse of this address signal change detection circuit. including,
M, O characterized in that a function is added to stop the sending of the detection pulse by a signal from a predetermined external terminal.
S static type RAMu 2, the memory cells constituting the MOS static type RAM are information storage MOS FETs whose gates and drains are cross-connected, and an information storage MOS FET provided between each drain and the power supply voltage. 2. The MOS static type RAM according to claim 1, further comprising a high resistance means for the MOS static RAM.