JPS60253255A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS capacitor having a large capacity with only adding a simple process to the filling process for an etching recess by a method wherein at least one dielectric layer and an electrode layer are formed on the gate electrode, and this electrode layer and the semiconductor substrate are made to come into contact. CONSTITUTION:An etching hole 2 and a gate dielectric layer 3 are formed in a semiconductor substrate 1, and after that, a gate electrode 4 is deposited. After that, a gate dielectric layer 6 is formed on the surface of the polycrystalline silicon gate electrode 4 by performing a thermal oxidation, for example. A contact hole 9 is opened. Moreover, when a polycrystalline silicon electrode layer 7 containing phosphorous is deposited on the upper surface thereof, a difffusion layer 8 is automatically formed in the part of the hole 9 and the semiconductor substrate 1 is made to come into contact with the polycrystalline electrode layer 7. A filling material layer 5 is deposited and an etcing is prformed on the filling material leyer 5 to remain the filling material layer in only the part of the hole 2. After that, the polycrystalline electrode layer 7 is etched in the prescribed form.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a MO
The present invention relates to a semiconductor device having an 8-type capacitor.

[Prior art]

There is a conventional MO8 type capacitor shown in FIG.

In Fig. 1 <a> to (g), 1 is a semiconductor substrate, 2
3 is an etching hole, 3 is a gate dielectric layer, 4 is a gate electrode made of polysilicon, etc., and 5 is, for example, a plasma nitride film or a plasma oxide film #CVD (Chemical V
apour deposition) An insulating material such as an oxide film or a filling layer that is heat resistant and easily plasma etched such as CVD polysilicon.

Next, a conventional method for manufacturing a semiconductor device is shown in FIGS. 1(a) to (g).
).

At a predetermined position of the semiconductor substrate 1 as shown in FIG. 1(a), an etching hole 2 is made as shown in FIG. 1(b) using a normal photolithography technique and an etching technique using Freon gas plasma. . Then, on the surface of the etching hole 2,
A gate dielectric layer 3 is formed as shown in FIG. 1(C). As the gate dielectric layer 3, a thermally oxidized silicon film, a thermal silicon nitride film, a silicon nitride film formed by low pressure CVD, or a composite thereof is standard. Next, on top of that
A gate m[ ] 114 (for example, made of CVD polysilicon containing phosphorus or the like) is formed as in dJ, and a filling layer 5 is deposited thereon as shown in FIG. 1(e). Thereafter, as shown in FIG. 1(f), this filling layer 5 is plasma-etched to the extent that the entire layer other than the portion of the etching hole 2 is removed, and then, as shown in FIG. 1(g), normal photolithography is performed. When the gate electrode 4 made of polysilicon is etched into a predetermined shape using technology,
Gate dielectric layer 3 between semiconductor substrate 1 and Goo'444
A MOS capacitor having a sandwiched shape is completed.

Conventional MOS capacitors are constructed as described above, so in order to increase the capacitance while keeping the same occupied area, it is necessary to reduce the thickness of the gate dielectric layer 3 or increase the depth of the etched hole 2. Therefore, there was no choice but to increase the effective area, but the former cannot be made less than 100A from the viewpoint of reliability, and the latter requires that the depth of the etching hole 2 be 5 to 6 μm from the viewpoint of reliability and the ability of the etching equipment. However, since there is a limit to this, there is a drawback that it is impossible to achieve a capacity higher than a certain limit.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional method as described above, and by adding a device to the process of filling the recesses by etching, it is possible to eliminate the disadvantages of the conventional method without increasing the occupied area.
．． An object of the present invention is to provide a MOS type semiconductor device having a capacitance that is five times or more larger.

An embodiment of the present invention will be described below with reference to the drawings.

[Embodiments of the invention]

FIGS. 2(a) to (i) are cross-sectional views of the manufacturing process for explaining one embodiment of the present invention, in which 6 is a gate dielectric layer, 9 is a contact hole, and 1 is a layer in which, for example, phosphorus or the like is mixed. The polysilicon electrode layer 8 is a diffusion layer. Note that the other parts are the same as in FIG. 1.

In this invention, first, FIG. 2 tab (b).

As shown in (C), after forming the semiconductor substrate IK etching hole 2 and the gate dielectric layer 3 in exactly the same manner as in the conventional method, the gate dielectric layer 3 is formed. A polysilicon gate electrode 4 is first formed into a predetermined shape pattern by depositing IA 4 or by conventional photolithography and etching. After that,
As shown in FIG. 2(d), this polysilicon gate electrode 4
A gate dielectric layer 6 is formed on the surface, for example by thermal oxidation. Next, as shown in FIG. 2(e), a contact hole 9 is formed at a predetermined position using conventional lithography and etching techniques. Furthermore, when a layer 1 of polysilicon containing phosphorus is deposited on the upper surface as shown in Fig. 2(f), a diffusion layer 8 is automatically formed in the contact hole 9, and a layer 1 of polysilicon containing phosphorus is automatically formed in the contact hole 9.゛Contacted with layer 1 of 44. Next, as in the conventional method, a filling layer 5 is deposited as shown in FIG. Then, by etching the polysilicon 11t pole layer 1 into a predetermined shape using ordinary photolithography and etching techniques, a KMO8MOS capacitor is obtained as shown in FIG. 2 (+).

In this new structure, a capacitor is formed between the gate electrode 4 and the underlying silicon semiconductor substrate 1;
The capacitance created by the gate dielectric layer 6 is also added between the gate dielectric layer 1 and the electrode layer 1, and a large capacitance can be realized with approximately the same occupied area as in the conventional method.

In the above embodiment, the silicon semiconductor substrate 1 under the gate dielectric layer 3 is not diffused, but in other embodiments, as shown in FIG. By providing the n-diffusion layer 10 and the p-diffusion layer 11, an even larger capacitance can be achieved.

In each of the above embodiments, a two-layer case in which the electrode layer 1 is provided on the *4 is shown, but this can also be expanded to three or more layers.

[Effects of the Invention] As explained above, (1) the present invention provides an etching hole in a semiconductor substrate by an etching process, and forms a layer (94) of goo on the inner surface of the etching hole.

In the semiconductor device in which a gate electrode is provided on the gate electroelectric layer, at least one dielectric layer and an electrode layer are formed on the gate electrode, and the electrode layer and the semiconductor substrate are in contact with each other. Therefore, by making simple additions to the etching recess filling process, it is possible to create a MOS with a large capacity.
It has the advantage of being able to form a capacitor.

[Brief explanation of drawings]

FIGS. 1(a) to (g) are cross-sectional views showing the manufacturing process of a conventional semiconductor device, and FIGS. 2(a) to Ci) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor device showing another embodiment of the invention. In the figure, 1 is a semiconductor substrate, 2 is an etching hole, 3 is a gate dielectric layer, 4 is a gate electrode, 5 is a filling layer, 6 is a gate dielectric layer, 7 is an electrode layer, 8 is a diffusion layer, and 9 is a diffusion layer. It is a contact hole. In addition, the same symbols in the diagram indicate the same or equivalent parts ◎ Agent Masuo Oiwa (2 others)

Claims (1)

[Claims] forming an etching hole in the semiconductor substrate by an etching process, forming a gate dielectric layer on the inner surface of the etching hole;
A semiconductor device in which a gate electrode is provided on the gate dielectric layer, characterized in that at least one dielectric layer and an electrode layer are formed on the gate electrode, and this layer is in contact with the semiconductor substrate. semiconductor device.