JPS60254355A - Cross call control system - Google Patents

Abstract

PURPOSE:To attain the cross call control of I/O control devices by connecting the I/O control devices through two multiplexer channels and two independent communication routes and using plural subchannels defined in respective communication routes. CONSTITUTION:If the switch state of an IFS control circuit 29 is set to neutral, it is checked that a bit in a TAGO.A register 23 which indicates the state of an output pipe line A is ON and a starting address in a BUSO.A register 26 is checked. When the starting address is included within a defined subchannel range, the IFS control circuit 29 is set to the A side, an ISA bit indicating the starting sequence of a TPSR33 is turned on and a microprocessor 18 is interrupted. The microprocessor 18 is started by a program to send information to a control program in a communication control device and store the data written in the BUSO.A register 26 in a local storage part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a control method for an input/output control device, and particularly to a cross-call control method for an input/output control device connected to a multiplexer channel and using a plurality of subchannels.

[Conventional technology and problems]

The input/output control device is located between the input/output device and the central processing unit and is responsible for transferring data between the two, specifying the input/output device, and specifying operations. A communication control device (CC
P) is used. The communication control device ccp will be explained below as an example.

As shown in FIG. 5, the communication control device CCP connects multiplexer channel MXC and selector channel SLC (not shown) on the host CPU side via channel adapter CA.
It is connected to the communication line and the terminal device TE via the line scanning mechanism C8. IF-A and IF-B are interfaces that are communication routes for multiplexer channels MMC-A and MMC-B, CC is a central control unit that controls the operation of the communication control device ccp, and MS is a storage unit in which control programs NCP and messages are stored. This is the main memory where the main memory is located.

A conventional communication control device CCP controls multiplexer channel MMC and selector channel SL via an interface.
In this case, when using a single dehice address, cross call control, i.e. the fifth
In the figure, two interfaces IF-A and IF-B
The two multiplexer channels MXC-A and MXC
-B, it is possible to control calls from either multiplexer channel, but when multiple subchannels are used with multiplexer channel MXC, cross-call control is not possible. there were.

In such a case, conventionally, as shown in FIGS. 5A and 5B, two multiplexer channels MXC-A or MX(,-B are connected to
The disadvantage is that one must be selected and used in a fixed manner. This was also true for other input/output control devices.

[Purpose of the invention]

The purpose of the present invention is to improve the shortcomings of conventional input/output control devices, and to make possible a loss call control method for input/output control devices using multiplexer channel connections and using multiple subchannels, in particular using a byte multiplexer as a multiplexer channel. The present invention also provides a loss call control method suitable for an input/output control device using a plurality of subchannels.

[Structure of the invention]

In order to achieve the above object, the present invention provides an input/output control device that operates by connecting two multiplexer channels and two independent communication routes and using a plurality of subchannels defined for each of these communication routes. The cross-call control method includes a storage means for storing identification information of the communication route corresponding to the plurality of subchannels, and a storage means for storing identification information of the communication route by detecting a startup sequence from the multiplexer channel. means for transmitting data to a storage means; means for retaining information stored in the storage means until the termination status transfer to the subchannel is completed; By including means for determining a communication route with a multiplexer channel, cross-call control of an input/output device connected to a multiplexer channel and using a plurality of subchannels can be effectively performed.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail by taking the communication control device ccp as an example. FIG. 1 shows a communication control device CC according to the present invention.
This figure shows an example of the circuit configuration of the channel adapter CA portion of P.

The communication control device of the present invention is an input/output control device with a built-in control program, and the channel adapter CA in charge of channel interface control is microprogram controlled.

These basic configurations and control operations are the same as those of conventional communication control devices with built-in control programs.
A is middle lc, Yumiko explains.

In FIG. 1, a local storage unit (LS) 11 is used as a data area corresponding to input/output commands from the control program NCP and a work area for a microprogram for the channel adapter CA. 12 is a local storage unit address register (LS
AR), 13 is an address decoder (AD), 14 is a local storage data register (LSDR) into which data read from the local storage 11 is temporarily written;
15 and 16 are input/output buses, 17 is an input/output control bus (IOC, -BUS) control circuit that performs cycle steal control, 18 is a microprocessor (MPU) that controls the channel adapter CA with a microprogram, and 19 is a control circuit. A control program storage unit (CM) in which the microprogram MP is stored, 20 surrounded by a dotted line is a cross-call control unit.

In the cross call control unit 20, reference numeral 21 denotes an interface A (IF-A) that performs reception and driving on a communication route for multiplexer channel A (MXC-A).
), 22 is the multiplexer channel B (MX, (, -
23 is an output tag A (TAGO・A) register that stores output tag information from MXC-A transferred from IF-A 21; 24 is IF-B
Output tag B (TAGO-B,) register 25 that stores output tag information from MXC-B transferred from 22
26 is an input tag (TAGI) register that stores input tag information transferred from the communication control device ccp; 26 is an IF-A
Output bus data A (BU
SO・A) Register 27 is output bus data B (I3USO-B) that stores output bus data such as MXC-B address and command transferred from IF-B22.
28 is an input bus data (BUSl) register that stores input bus data such as response data and status from the communication control device CCP; 29 is IF・A and 1F;
An interface switch (IFS) control circuit for -B, SWA and SWB located at various locations are switches whose opening and closing are controlled by the switch control circuit 29, and 30 to 32 are OR circuits. TAGO・A register 23, TAGO-B
Register 24, TAGl register 25, BUSO.A register 26, BUSO.B register 27, and BUS I register 28 are registers for channel interface.

33 is 2 processor switch register (TPSR)
This is a register for exchanging control information between hardware and firmware regarding cross calls, and its bit definition is shown in FIG.

In Figure 2, initial selection A (ISA
) bit turns on when a channel command is received from IF-A, and the initial selection B (ISB)
The bit turns on when a channel command is received from I'F-B, and the center/neutral focus is
It turns on when returning to neutral from the switch status of -A or IF-B, the switch A (SW-A) focus turns on when forcing the switch to I'F・8, and the switch B (SW・B) bit turns on. Turns on when forcibly switching to IF-B.

Next, the cross-call operation shown in FIG. 1 will be explained.

Now, the startup sequence in which a channel command is issued from MXC-A is sent to channel adapter CA via IF-A.
Suppose we reach . This turns on the upper bit of the TAGOi A register 23, which indicates that the output tag line A is on.

At this time, assuming that the switch state of the I'F S control circuit 29 is neutral, first [Fs control circuit 29
Check that the bit indicating the status to the output tag line on the TAGO-A register 23 is on, and then
The activation address information on the A register 26 is checked. If the activation address is within the subchannel range defined in the communication control device CCP, the switch state of the IFS control circuit 29 is set to the A side and each switch SW
A is turned on, and the ISA bit indicating the start-up sequence on the T)) S R33 is turned on to interrupt the microprocessor 18.

The microprocessor 18 starts the startup sequence using the microprogram MP and notifies the control program NCP of the communication control device CCP.

Next, the microprocessor 18 reads the activation address and channel command sent from the MXC-A and written in the BUSQ/A register 26, and stores them in the local storage section 11. The series of operations while reading the activation address and channel command sent from MXC-A and written in the BUSO-A register 26 are as follows: TAGO-A, T
AGO-B, TAG-I, BUSO-A, BUSO-B
The operation is similar to the well-known channel interface operation using each register, and a detailed explanation thereof is not necessary for understanding the cross-call control operation of the present invention, so a detailed explanation thereof will be omitted.

FIG. 3 shows the focus definition of the cross-call control area of the local storage unit 11. The cross-call control area actually has 256 addresses corresponding to the total number of subchannels, but in the figure, from address 100 to IFF address 16 in hexadecimal, it corresponds to subchannels X "00" to "FF". Addresses are associated. INTF-A and I
Each bit of NTF-B is MMC-A and MXC-B
Each is turned on when a call is made. The microprocessor 18 inputs the BUSO-A register 26 to MX
When storing the startup address of C-A in the cross call control area of the local storage unit 11, the BUSO・A register 26
A local storage address is created based on the information, and the INTF A bit is turned on to write to the local storage unit 11.

Thereafter, the microprocessor 18 changes the startup status to M
The data is transferred to the XC-A, the startup sequence is ended, and an interrupt is placed on the control program NCP of the communication control device CCP.

At this time, the status bit on the TAGI register 25 (
(not shown) is turned on. When the control program NCP receives an interrupt, it sets the transfer address to the channel in the local storage unit 11.

Once the startup sequence is complete, the microprocessor 18
clears the TAGI register 25 and controls the interface switch according to the channel command. That is, in the case of a command that does not involve data transfer, the IFS control circuit 29 is commanded to reset the INTF-A bit of the local storage section 11, turn on the cent/neutral bit of the TPSR 33, and return the switch state to neutral. On the other hand, in the case of a channel command that involves data transfer, the same switch state, ie, SWA, needs to be maintained, so the switch control as described above is not performed.

In this case, the INTF.A bit on the local storage unit 11 is held until the data transfer and status transfer are completed.

For data transfer and status transfer instructions after an interrupt to the control program NCP due to the startup sequence, the corresponding address in the cross-call control area is referred to based on the transfer address in the local storage unit 11 set by the control program NCP. information on which interface to transfer the data to. In the case of the example,
INTF-A is on. The microprocessor 18 is configured as follows:
3(7) Turn on SW-A, send a request-in signal, and start the transfer sequence.

After completing the data transfer and final status transfer, the MM
Since the cross-call control information on the local storage unit 11 regarding C-A is no longer necessary, the termination status is set to MX(,
- After being received by A, the microprocessor 18
Turn on the set neutral bit on R33 and set 5
Reset the W-A bit, return the interface from interface A to the neutral state, and end execution of the channel command.

The above describes how interface A' (I
We have explained the case where the activation from neutral to interface B (IF-8
22), a similar control procedure is used to execute the startup sequence and the channel sequence such as the channel command.

Note that if interface B (IF-B22) is activated by interface A (IF-A21) while the channel sequence is in a switched state, or vice versa, the This is similar to the commonly used cross-call control method.

In the cross-call control method of the present invention, as illustrated in FIG. 4, a cross-call control operation is performed when a hide multiplexer is used in the multiplexer channel MXC.

Figure 4 shows three subchannels 5ubCH1 to 5ubC.
Taking H3 as an example, an example of cross call control operation is shown when byte multiplexers are used as MMC-A and MXC-B.

In the figure, the upper part is interface A (IF-A21)
, the lower part shows the interface B (IF-B22), Is shows the startup sequence, DT shows the data transfer cycle, and ST shows the termination status transfer cycle. Subchannel 1 is T
Activate interface A at I3.I
The first channel sequence is completed by transferring data at line 5 and transferring the termination status at line 61T7. Then T'+
Activate interface B at 2, transfer data at TI4, transfer the final status at 1゛1o, and start the second interface.
End the channel sequence for the second time. sub channel 2
activates interface A at I4, transfers data at I9, transfers termination status at To, and ends the first channel sequence. Next, activate ink face B using TIE, transfer data using TIB, and then
At step 211, the termination status is transferred to end the second channel sequence. Subchannel 3 activates interface B at I2, transfers data at I6 and Te, and transfers termination status at T'+o, thus completing the first channel sequence. Next, T13 activates interface A, TI5 transfers data, and TI7
The end status is transferred and the second channel sequence ends.

Although the above explanation has been given using a communication control device as an example, the cross-call control method of the present invention is not limited to the case of a communication control device, and can also be used for cross-call control methods of other input/output control devices. It is something that can be done.

〔Effect of the invention〕

As explained above, according to the present invention, cross-call control is possible even in an input/output control device that is connected to a multiplexer and uses multiple subchannels. In particular, when a byte multiplexer is used as a multiplexer channel, each subchannel Since channels are given an equal opportunity to start up, a successful loss call can be performed.

Furthermore, the total throughput seen as a system is improved, and even in the event of a channel failure, it becomes possible to automatically select a bus, thereby improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a circuit configuration of a channel adapter in a communication control device which is an embodiment of the cross control method for an input/output control device according to the present invention, and FIG. 2 is an explanatory diagram of a circuit configuration of a channel adapter used in the channel adapter of FIG.・Switch register (
An explanatory diagram of the bit definition of TPS, R), Figure 3 is the local storage unit (LS) used in the channel adapter in Figure 1.
FIG. 4 is an explanatory diagram of the operation example of FIG. 1, and FIG. 5 is an explanatory diagram of a conventional communication control device. 11...Local storage unit (LS), 12...
...Local storage address register (LSAR)
, 13...address recorder (AD), 14.
...Local storage data register (LSDR)
, 15. 16... Input/output bus, 17... Input/output control bus (iocmBUS) control circuit, 18...
・Microprocessor (MPU), 19...
Control program storage unit (CM), 20...Cross call control unit, 21...Interface A
(IF-A), 22...Interface B
(IF-B), 23... Output tag (TAGO
・A) Register, 24... Output tag B (TA
GO/B) Register, 25...Group/Input tag (TAGI)
) register, 26... Output bus data A (B
USO/A) register, 27... Output bus data (BUSO/B) register, 28/Old... Input bus data (BUSI) register, 29... Interface switch (IFS) control Circuit, 30-32...
...OR circuit, 33...2 processor switch register (TPSR). Patent applicant Fujitsu Ltd.

Claims (2)

[Claims] (1) Connected by two multiplexer channels and two independent communication routes, using multiple subchannels defined for each communication route. A cross-call control method for an input/output control device that operates using a storage means for storing identification information of the communication route corresponding to the plurality of subchannels, and detecting a startup sequence from the multiplexer channel. means for transmitting the identification information of the communication route to the storage means; means for holding the storage information in the storage means until the termination status transfer for the subchannel is completed; 1. A cross-call control method for an input/output control device, comprising means for determining a communication route with a multiplexer channel by referring to information stored in a storage means. (2) The cross-call control system according to claim 1, wherein the two multiplexer channels are byte multiplex signals.