JPS60257570A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce noises, and to improve high-frequency characteristics largely by simply forming all of each element through self-alignment. CONSTITUTION:Polysilicon 2 is deposited on an N type silicon substrate 1, and silicon oxide is shaped onto polysilicon 2. A nitride film 4 in width slightly larger than emitter width is formed through photoetching, and etched until side etching sections (t) in small width are shaped on both sides of the lower section of the nitride film 4. P layers are formed in the substrate just under the side etching sections (t) and P<+> layers in regions as external base layers on both sides of the nitride film by implanting boron 6 as impurity ions. When the P<+> layers and the P layers are diffused through selective oxidation, the nitride film 4 is removed and boron 6' is implanted again, boron passes in the substrate, and a P<-> layer in low concentration is shaped. The whole is etched only by the thickness section of silicon oxide 3 as the upper section of the P<-> layer and arsenic ions as impurity ions, which must function as an emitter layer to the P<-> layer, are implanted, a window for the contact of a P<+> base is bored, and Al is wired, thus forming a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Al technical field) This invention relates to a semiconductor device including a bipolar transistor,
In particular, the present invention relates to a method of manufacturing a semiconductor device in which base and emitter regions are formed by self-alignment.

(bl Prior Art and Its Disadvantages In the typical method of manufacturing bipolar transistors,
The collector and base are placed on a silicon substrate by repeating the diffusion and photoetching steps.

Each region of the emitter is formed. but,
Since this method uses a mask for alignment, highly accurate alignment is required, and when manufacturing low-noise, high-frequency transistors, it is necessary to set a certain amount of allowance for alignment. However, due to the allowance, it was not possible to reduce the emitter width beyond a certain level, and there was a limit to the ability to manufacture high-performance, low-noise, high-frequency transistors. Therefore, in order to solve this problem, many methods have been proposed and implemented that use polycrystalline silicon to perform alignment using self-alignment lines, but none of these methods have been used for alignment for emitter contact. Emitter width, emitter contact area, and emitter contact area are important elements for performance improvement in a series of manufacturing processes.
External base layer (P layer) to reduce Heas resistance
It was not possible to form everything with Selfa Line.

(C1 Purpose of the Invention The purpose of the present invention is to provide a method for manufacturing a semiconductor device in which all of the above-mentioned elements can be easily formed using a self-alignment line.

(d+ composition of the invention t Figures 1 (A) to (G) are high □ FIG. 3 is a diagram illustrating a polar transistor manufacturing method in order of steps.

This manufacturing method will be described in detail below in order of steps.

(1)--FIG. 1(A) Polysilicon (polycrystalline silicon) 2 is deposited on an N-type silicon substrate 1 by the CVD method. Furthermore, silicon oxide (Si0z) is formed on the polysilicon 2 by CVD or thermal oxidation. After that, a nitride film (s) with a width slightly larger than the emitter width of the transistor to be manufactured is
i3N4)4 is formed by CVD and photoetching.

(21---Figure 1(B) Wet etching is performed using a resist 5 that defines the outside of the external base layer and has an opening in the portion that will become the transistor region.At this time, wet etching is performed on both sides of the bottom of the nitride film 4. Etch until a narrow side etched portion t is formed.

+31-11 Figure 1 (C) Boron 6, which is an impurity ion, is implanted. By appropriately selecting the energy during ion implantation, a P layer is formed in the substrate directly under the side etched portion t of the nitride film 4, and an external base layer is formed on both sides of the nitride film. A layer is formed (4) - FIG. 1(D) The resist 5 is removed and selective oxidation is performed. At this time, the P layer and the P layer are diffused within the substrate as shown in the figure, and a bird's beak 7 is formed in the silicon oxide 3.

(5)-Figure 1 (E) The nitride film 4 is removed by etching and the boron 6' is etched again.
ion implantation. In this case, the removed nitride film 4
In the lower substrate of the silicon oxide 3, boron only passes through the thin part, and holons do not pass through the other parts. The boron 6' that has passed into the substrate becomes a layer of low concentration P.

(6)-FIG. 1(F) The P layer is activated by annealing, and the entire silicon oxide 3 is etched by the thickness of the silicon oxide 3 above the P layer.

(7)-FIG. 1(G) Arsenic, which is an impurity ion to become an emitter layer, is ion-implanted into the P layer. Furthermore, annealing treatment is performed thereafter to activate and diffuse.

After this, we opened a window for P1 hair contact,
A7! Wiring is performed to form a transistor. In this case, the AN wiring for the emitter is formed on the polysilicon 2.

(d1 Effects of the invention As described above, according to this invention, the following effects can be achieved.

(1) By forming the P'' heath layer and P base layer for the emitter layer using self-line, it is possible to form a P'' layer with a low resistance near the heath contact, so the heath resistance becomes extremely small. Since a single layer of low-concentration P can be formed in the vicinity of the Hose emitter junction, the capacitance between the Hose emitter junction and the emitter junction is also reduced, making it possible to fabricate a low-noise transistor.

(2) Since the emitter layer and emitter contact are also self-aligned, fine processing of the emitter is possible and high frequency characteristics are greatly improved.

(3) Masks for nitride film etching,・It has the advantage of being able to create runcisters.

[Brief explanation of drawings]

FIGS. 1A to 1G are diagrams illustrating a method for manufacturing a hyperpolar transistor according to the present invention in order of steps. Applicant ROHM Co., Ltd. Agent Patent Attorney Hisao Komori Figure 1 (A) (C) ↓ ↓ ↓ ↓ I 111 ↓ I Figure 1 (G)

Claims (1)

[Claims] (After forming polysilicon and a nitride film on an 11N type silicon substrate, the nitride film is photo-etched so that the width is slightly larger than the emitter width and small width side etched portions are formed on both sides of the lower part of the nitride film. Then, by implanting impurity ions, a P layer is formed in the substrate directly under the side etched portion, and a P layer to be an external base layer is formed on both sides of the nitride film, and the P layer and the P layer are formed by selective oxidation. After diffusing the nitride film, the remaining nitride film is removed and impurity ions are implanted into the substrate below to form a P layer that will become an internal base layer.Then, the entire oxide film is removed by the thickness of the oxide film on top of the P layer. A method of manufacturing a semiconductor device, comprising: etching; further implanting impurity ions into the P layer to form an emitter layer; then opening a window for a P4 base contact and forming metal wiring.