JPS6026477A - Drive circuit - Google Patents

Abstract

PURPOSE:To prevent a transistor from damaging at normal/reverse switching time by temporarily turning OFF all the transistors of a transistor bridge circuit in response to the variation of a control signal. CONSTITUTION:When the level of a signal A0 or A1 varies, a detector 14 detects the variation in the level of the signal A0 or A1 and outputs a differentiation signal B. A monostable multivibrator 26 is triggered by the signal B, and outputs a ''1'' level signal of the prescribed pulse width. Accordingly, the output of a decoder 12 becomes 0000, and transistors 36-41 of the transistor bridge circuit are turned OFF. When the output signal A1 of the multivibrator 26 becomes ''0'' after the prescribed time, the outputs D1-D3 of the decoder 12 becomes the prescribed state. Thus, excess current is not flowed to the transistors at the normal/reverse switching time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit, and particularly to a drive circuit that drives a driven object using a transistor circuit configured as a bridge.

Conventionally, in order to drive a bt magnetic solenoid or a reversible motor, etc., a transistor is connected to a bridge and the direction of the current flowing through the output section is changed to the forward or reverse direction. It is being

However, in conventional drive circuits, during forward/reverse switching, due to unevenness in the ON and OFF times of transistors, a large current flows through the load, albeit for a short time, and a large current flows through the circuit due to the unevenness of the ON and OFF times of the transistors. There is a drawback 75E that the transistor is destroyed by this large current during use.

Therefore, an object of the present invention is to provide a drive circuit that prevents an undesired large current from flowing through a transistor during forward/reverse switching.

The present invention will be described in detail below with reference to the drawings.

According to the circuit shown in Figure 1, a control circuit (
Terminals Ao and A1 of the CPU (for example) 11 are terminals A of the decoder (for example, the PROM) 72.

and A1. A runaway detection circuit 13 is connected to the control circuit 11 to detect runaway of the control circuit 1 .

The output terminal of the control circuit 11 is also connected to a signal change detection circuit 14 that detects changes in the control signal. In this detection circuit 14, terminals AO and A1 are directly connected to one terminals of capacitors 15 and 16, respectively, and are connected to one terminals of capacitors 19 and 20 via inverters 17 and 18, respectively. The other terminals of capacitors 15, 16, 19 and 20 are connected to the resistance connection points of series resistance circuits 21, 22, 23 and 24, respectively, and to the input terminal of AND gate 250. The output terminal of the AND dart 25 is connected to a monostable multivibrator 26. The output terminal of the monostable multivibrator 26, ie, the output terminal of the detection circuit 14, is connected to the terminal A2 of the decoder 12. The output terminal of the runaway detection circuit 13 is connected to the terminal A3 of the decoder 12. The output terminals DO, Ds, 1) of the decoder 12
2 and Ds are the resistors 2F of the transistor Britno circuit 27.
+, 29, 30 and 31, respectively. The other ends of resistors 2B, 29.30 and 3I are transistors 32,
33, 34 and 35 paces respectively. The emitters of transistors 32-35 are grounded, and the collectors of transistors 32 and 33 are connected to the paces of transistors 38 and 39 via resistors 36 and 37, respectively.

The collectors of transistors 34 and 35 are transistor 4
Connected to paces of 0 and 4 respectively. transistor 3
The collector of transistor 39 and the emitter of transistor 8 are connected to each other and to one end of solenoid 42, and the collector of transistor 39 and the emitter of transistor 41 are connected to each other and to the other end of solenoid 942.

In the P live circuit described above, the decoder 12 is configured to decode the input signal according to the following relationship.

Therefore, a signal A as shown in FIG. 2 is generated from the control circuit 11.

and A1 are output, the drive circuit operates as follows. That is, when the signals AO and A1 are constant at 1.1, the output signal B of the AND dart 25 is constant;
The output signal A2 of the monostable multi 26 is at the O level. At this time, if the output signal A3 of the runaway detection circuit 13 is at the 0" level indicating non-runaway, the decoder 12 outputs the signal υ according to the above table.
Outputs oooo. In this case, none of the transistors 32 to 35 are turned on. That is, solenoid 42 is not energized.

When the signal Ao changes to 0 level, the detection circuit 14 outputs the signal Ao.
Detecting the level change of o, output signal B of AND gate 25
becomes a differential signal as shown in FIG. The monostable multi 26 is triggered by this signal B, and a constant pulse width of 11
#Output level signal. Therefore, the input to the decoder 120 remains 0110, its output remains 0000, and the p-transistors 32 to 35 are kept OFF. When the output signal A2 of the monostable multi 26 reaches the "0" level after a certain period of time, the inputs Ao to A3 of the decoder 12 are outputted as 0100.

D3 becomes 1001. As a result, transistor 3
2 and 35 are not ON, and accordingly transistor 3
8 and 41 are turned ON. Therefore, transistor 38,
A current flows through the solenoid 42 and the transistor 41, and the solenoid 42 is excited in the positive direction. In this state, when the control signal A1 of the control circuit 1 reaches the "0" level as shown in FIG. Birds play multi 26. Therefore, the decoder has 120 inputs.

From A3, the output Do becomes p-,010 for a certain period of time.
D3 becomes 0000. Therefore, monostable multi 26
At time constant 0, transistors 32 to 35 and 36, 37, 40 and 41 are all turned off. That is, even if there is some variation in the ON and OFF times of these transistors, the ON signal is not supplied until all transistors are completely OFF. That is, the ON signal is not supplied until the transistors 32r35+38 and 4, which were turned on in the above operation, are completely turned off. The signal A2 of the monostable multi 26 becomes ``0'' after a certain period of time.
” level, the input AO to AsFi of the decoder 12
The outputs Do to D8 become 0110. Therefore, when transistors 33 and 34 are turned on, transistors 39 and 40 are turned on accordingly. Lately,
The excitation current flows in the opposite direction through the transistor 3g, the solenoid 42, and the transistor 4σ, and the solenoid 42 is excited with the opposite polarity.

Next, the output signal A of the control circuit 1. IAI is both l”
When the level is reached, the outputs Do to D8 of the decoder 12 become 0000.
and 4o is turned off. That is, all transistors are turned off.

After this, it returns to the initial state. Note that even if the control circuit 11 goes out of control during the operation of the drive circuit and the runaway detection circuit 13 outputs a runaway detection signal of "1" level, the transistor circuit 27 is turned off.

Next, another embodiment will be described with reference to FIG. In this embodiment, the output terminal Ao of the control circuit 11 is connected to the decoder 11.
The output terminal AI is connected to the first input terminal of the AND darts 114 and 115 through the inverter 113ft of the second inverter 113ft.
It is connected to the second input terminal of the ND gate 114 and also to the second input terminal of the AND dart 115 via the inverter 116 . Further, terminals AO and Al are connected to differentiating circuits 119 and 120 via inverters 117 and 118 of the detection circuit 114, respectively, and are also directly connected to differentiating circuits 121 and 122. AND gates 123 and 124 are connected to the differentiating circuits 119 and 120,
OR darts 125 and 1 are connected to the differentiating circuits 121 and 122.
26 are connected. The output terminals of AND gates 123, 124 and OR dates 125, 126 are OR gate 1.
27 is connected to the input terminal. The output terminal of the OR dart 127 is connected to a monostable multivibrator 128.

The output terminal of the monostable multi 128 is ANDed through the inverter 129 of the decoder 112.
is connected to the third input terminal of. The output terminal of the runaway detection circuit 13 is connected to the AND dart 114 via the input terminal 130.
and 115 input terminals.

The output terminals of AND darts 114 and 115 are connected to the transistor bridge circuit 1 via inverters 131 and 132.
33.

The transistor Pritsuno circuit 133 includes four switching transistors 134, IJ, which are bridge-connected.
5, 1,? 6 and 137 are provided. Photocouplers 138 to 141 are connected to the paces of these switching transistors 134 to 137. The inputs of photocouplers 138 and 141 are connected to the output terminal of inverter 131 of decoder 112, and photocouplers 13g and 140 are connected to the output terminal of inverter 132.

A reversible motor 142 is connected to the output section of the transistor bridge circuit 133.

In the embodiment of FIG. 3, the signals Ao and A shown in FIG.
, is supplied, first the signals Ao, A, , A2
and hs are 1100, the output signals of AND darts 114 and 115 are OO, and therefore the photocoupler 13
8 to 141 are turned off, and accordingly, switching transistors 134 to 137 are turned off. Next, when the signal A0 reaches the "'0" level, the signal A
At the falling edge of o, the differential signal is supplied to the monostable multi 128 via the OR gate 127, and the monostable multi 128 outputs the signal A2 at the "'1" level for a certain period of time. Also in the case of jin, the outputs of AND darts 114 and 115 are OO. When signal A2 falls after a certain period of time, AND)t"-)1
The output of 14 and 115 is 10, and the photocoupler 138
and 14 are turned on, and accordingly transistor 1
34 and 137 are turned ON. Therefore, the drive current flows through the motor 142 in the forward rotation direction. In this state, when the signals AO+ and AI of the control circuit 1 become 0.0, the signal A1
At the falling edge of the signal A2, the signal A2 becomes the "1# level" and the output of the 1-delivery D dart 114 becomes the "0# level." Therefore, photocouplers 138, 141 and transistors 134 and 13
7 is OFF. Signal A2 returns to °'0 after a certain period of time.
'' level, the outputs of the AND gates 114 and 115 become Ol. Therefore, the photocouplers 139 and 140 are turned on, and the transistors 135 and 136 are turned on. Therefore, the driving current is applied to the motor 142 in the opposite direction. Flow motor 142 rotates in reverse.

Changes in the signal that controls the device are detected, and in response to this detection signal, all the transistors in the transistor bridge circuit are turned off, so when switching between forward and reverse driven devices, the transistor is switched off without passing through the driven device. Excessive current will not flow through the Zosta, preventing damage to the transistor. Accordingly, the power supply circuit is not deteriorated by overcurrent, and wasteful current consumption is suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a drive circuit according to one embodiment of the present invention, FIG. 2 is a time chart diagram for explaining the operation of the drive circuit, and FIG. 3 is a drive circuit according to another embodiment. FIG. 11... Control circuit, 12-... Decoder, 13...
Runaway detection circuit, 14... control signal change detection circuit, 27
...Transistor bridge circuit, 42...Solenoid, 112...Decoder, 114...Control signal change detection circuit, 133...Transistor bridge circuit, 1
42...Reversible motor. Applicant's agent Patent attorney Takehiko Suzue Commissioner of the Patent Office Kazuo Wakasugi 1. Indication of the case Japanese Patent Application No. 1983-135539 No. 2, Q″AQAQ Name 5'l'7, 8g3, Person making the amendment Relationship with the case Patent applicant (037) Kano Rinnosu Optical Industry Co., Ltd. Specification, Drawing 7, contents of correction

Claims (3)

[Claims] (1) A control signal output means for outputting a control signal for controlling a driven device that is driven in forward and reverse directions; and means for detecting a change in a control signal of the control signal output means and rendering all transistors of the transistor circuit non-conductive for a certain period of time. (2) The drive circuit according to claim 1, wherein the driven device is a magnetic solenoid connected to the output part of the transistor circuit means and driven in forward and reverse directions. (3) The drive circuit according to claim 1, wherein the driven device is a reversible motor connected to the output section of the transistor circuit means.