JPS6027196B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6027196B2 JPS6027196B2 JP55109943A JP10994380A JPS6027196B2 JP S6027196 B2 JPS6027196 B2 JP S6027196B2 JP 55109943 A JP55109943 A JP 55109943A JP 10994380 A JP10994380 A JP 10994380A JP S6027196 B2 JPS6027196 B2 JP S6027196B2
- Authority
- JP
- Japan
- Prior art keywords
- signal processing
- processing circuit
- chip
- photoelectric conversion
- conversion element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
この発明は半導体集積回路装置に係り、特に光電変換素
子部を内部に含む半導体集積回路装置の構成に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a semiconductor integrated circuit device that includes a photoelectric conversion element section therein.
光電変換素子と信号処理回路素子とを一体に集積した装
置では、当然のこととして、透明樹脂によるモールド、
または透明窓をもつ中空パッケージを用いることによっ
て光を内部の光電変換素子へ導入するようになっている
。In a device that integrates a photoelectric conversion element and a signal processing circuit element, it is natural to use transparent resin molding,
Alternatively, by using a hollow package with a transparent window, light is introduced into the photoelectric conversion element inside.
しかし、一般に１枚の半導体集積回路チップでは光電変
換素子部の受光面と信号処理回路素子部の能動領域側と
が同一主面側にあるので、信号処理回路素子部へも入射
光が侵入して、不要な光起電力を発生したり、リーク電
流を増大させ、誤動作、特性の劣化をもたらすおそれが
あった。However, in general, in a single semiconductor integrated circuit chip, the light-receiving surface of the photoelectric conversion element section and the active area side of the signal processing circuit element section are on the same main surface, so that incident light may also enter the signal processing circuit element section. This may generate unnecessary photovoltaic force or increase leakage current, leading to malfunction and deterioration of characteristics.
このため従来は、透明モールドパッケージの一部のみを
残して他の部分を光しやへし、する方法、中空パッケー
ジの内部に光しやへし、のためのカバーを組込む方法、
半導体集積回路チップの信号処理回路素子部の表面にア
ルミニウム膜などの薄膜を被覆する方法などがとられて
きた。しかし、これらの方法は組立て工程、またはゥェ
ハ製造工程が複雑となり、工数の増大、並びに製造の歩
蟹りおよび動作信頼性の低下の問題があった。この発明
は以上のような点に鑑みてなされたもので、光電変換素
子部と信号処理回路素子部とを分割して〜信号処理回路
素子部を裏返し｝こ取りつけることによってｔ光電変換
素子部への入射光が信号処理回路素子部の能動領域側へ
入射せぬようにして、簡単な構造で、動作信頼性の高い
半導体集積回路装置を提供することを目的とする。第１
図ａはこの発明の一実施例を示す側面図、第１図ｂは第
蔓図ａのＩＢ線における断面図で、しま光電変換素子チ
ップ〜 ２は信号処理回路素子チップ「３はリードフレ
ーム、４はボンディングワイヤ、５はモールド透明樹脂
である。図示のように光電変換素子チップ角と信号処理
回路素子チップ２とに分割して、光電変換素子チップー
はその受光面を上にしてリードフレーム３の上に装着し
て所要のボンディングワイヤ４による接続をし、一方、
信号処理回路素子チップ２はフリップチツプによるリー
ドフレーム３へのフェイスダウンボンディング方式が採
用されている。第２図ａはこの発明の他の実施例を示す
縦断面図、第２図ｂは第２図ａにおけるＯＢ−ＯＢ線で
の断面図で、第２図ａは第２図ｂにおけるＤ＾，Ｄ＾線
での断面に相当する。For this reason, conventional methods include methods of leaving only a part of the transparent mold package to protect the other parts from light, and methods of incorporating a cover inside the hollow package to provide light protection.
A method has been adopted in which the surface of a signal processing circuit element portion of a semiconductor integrated circuit chip is coated with a thin film such as an aluminum film. However, these methods require complicated assembly processes or wafer manufacturing processes, resulting in increased man-hours, slow manufacturing steps, and reduced operational reliability. This invention has been made in view of the above points, and by dividing the photoelectric conversion element section and the signal processing circuit element section and attaching the signal processing circuit element section upside down, it is possible to attach the photoelectric conversion element section to the photoelectric conversion element section. An object of the present invention is to provide a semiconductor integrated circuit device with a simple structure and high operational reliability by preventing incident light from entering an active region side of a signal processing circuit element section. 1st
Figure a is a side view showing one embodiment of the present invention, and Figure 1b is a cross-sectional view taken along the IB line of Figure a. 4 is a bonding wire, and 5 is a molded transparent resin.As shown in the figure, it is divided into a photoelectric conversion element chip corner and a signal processing circuit element chip 2, and the photoelectric conversion element chip is placed on a lead frame 3 with its light-receiving surface facing up. and connect it with the required bonding wire 4, while
The signal processing circuit element chip 2 employs a face-down bonding method to a lead frame 3 using a flip chip. Fig. 2a is a longitudinal sectional view showing another embodiment of the present invention, Fig. 2b is a sectional view taken along the OB-OB line in Fig. 2a, and Fig. 2a is a longitudinal sectional view showing another embodiment of the present invention. , corresponds to the cross section along the D^ line.
第竃図の実施例と同等部分は同一符号で示し、説明を省
略する。６ａは不透明中空パッケージ本体「 Ｓｂはそ
のふた、６ｃはふた６ｂに設けられた光入射用窓、７は
外部リード導体である。Components equivalent to those in the embodiment shown in FIG. 6a is an opaque hollow package body; Sb is a lid thereof; 6c is a light entrance window provided in the lid 6b; and 7 is an external lead conductor.
その組立て構造はパッケージの構造が異るのみで、その
他の点は第貴図の実施例と全く同一である。いずれの実
施例においても、信号処理回路素子チップ２はその能動
領域側表面が光入射側とは反対側を向いているので、光
電変換素子チップ亀への入射光が直接信号処理回路素子
チップ２の能動領域へ入射することがなくも誤動作など
の動作信頼性低下を生じることがない。Its assembly structure differs only in the structure of the package, and other points are exactly the same as the embodiment shown in FIG. In any of the embodiments, since the surface of the signal processing circuit element chip 2 faces the side opposite to the light incident side, the incident light to the photoelectric conversion element chip 2 is directly directed to the signal processing circuit element chip 2. Even if the light does not enter the active region of the active region, there will be no reduction in operational reliability such as malfunction.
中空パッケージの場合、信号処理回路素子チップをフェ
イスダウンボンディングする箇所のパッケージの底面を
反射率が小さくなるような処理を行っておけば、より有
効である。In the case of a hollow package, it is more effective if the bottom surface of the package where the signal processing circuit element chip is face-down bonded is treated to reduce the reflectance.
透明樹脂モールドの場合、若干の光まわり込みがあるが
、出来上った装置を黒色のプリント基板、ソケットへ装
着するなど、実装方法によって効果を向上させることが
できる。以上説明したように、その発明になる半導体集
積回路装置では光電変換素子チップと信号処理回路素子
チップとが分割された形で形成され、信号処理回路素子
チップを裏返してフェイスダウンボンディングしたので
、光電変換素子チップへの入射光が信号処理回路素子チ
ップの能動領域側へ入射することがなく、特別な光しや
へし、部材を設けることなく「誤動作などの動作信頼性
低下を防止できる。In the case of transparent resin molding, there is some light reflection, but the effect can be improved by mounting methods such as mounting the completed device on a black printed circuit board or socket. As explained above, in the semiconductor integrated circuit device according to the invention, the photoelectric conversion element chip and the signal processing circuit element chip are formed separately, and the signal processing circuit element chip is turned over and bonded face down. The light incident on the conversion element chip does not enter the active area side of the signal processing circuit element chip, making it possible to prevent operational reliability reductions such as malfunctions without the need for special light shields or members.
第１図ａはこの発明の一実施例を示す側面図、第１図ｂ
は第亀図ａのＩＢ−ＩＢ線における断面図、第２図ａは
この発明の他の実施例を示す縦断面図も第２図ｂは第２
図ａのＯＢ，ＯＢ線での断面図で、第２図ａは第２図ｂ
のＤＡ，ロ＾線での断面に対応する。
図において「 １は光電変換素子部のチップ、２は信号
処理回路素子部のチップ、５はモールド透明樹脂「 ６
ａは不透明中空パッケージ、６ｂはそのふた、６ｃは光
入射用窓である。
なお、図中同一符号は同一または相当部分を示す。鍵１
図
繁２図Fig. 1a is a side view showing an embodiment of the present invention, Fig. 1b
2 is a sectional view taken along the line IB-IB of FIG.
A cross-sectional view taken along the OB and OB lines in Figure a, and Figure 2 a is Figure 2 b.
Corresponds to the cross section along the DA and LO lines. In the figure, ``1 is a chip of the photoelectric conversion element section, 2 is a chip of the signal processing circuit element section, 5 is a molded transparent resin'' 6
a is an opaque hollow package, 6b is its lid, and 6c is a light entrance window. Note that the same reference numerals in the figures indicate the same or corresponding parts. key 1
Illustration 2
Claims (1)
明樹脂にてモールドされまたは上記光電変換素子部への
光入射用窓をもつ不透明中空パツケージに収容されたも
のにおいて、上記光電変換素子部のチツプと上記信号処
理回路素子部のチツプとが分割した形で形成され、上記
信号処理回路素子部のチツプがその能動領域側の面を上
記光電変換素子部のチツプの受光面とは反対方向にして
フエイスダウンボンデングされたことを特徴とする半導
体集積回路装置。1. A device having a photoelectric conversion element section and a signal processing circuit element section, and housed in an opaque hollow package molded with transparent resin or having a window for light incidence to the photoelectric conversion element section, wherein the photoelectric conversion element The chip in the signal processing circuit element part and the chip in the signal processing circuit element part are formed in a divided form, and the chip in the signal processing circuit element part has its active area side opposite to the light receiving surface of the chip in the photoelectric conversion element part. A semiconductor integrated circuit device characterized in that it is face-down bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55109943A JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55109943A JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5734375A JPS5734375A (en) | 1982-02-24 |
| JPS6027196B2 true JPS6027196B2 (en) | 1985-06-27 |
Family
ID=14523039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55109943A Expired JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027196B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6132480A (en) * | 1984-07-24 | 1986-02-15 | Canon Inc | Photosensor |
| JPH0444388U (en) * | 1990-08-10 | 1992-04-15 | ||
| JPH05110048A (en) * | 1991-10-14 | 1993-04-30 | Mitsubishi Electric Corp | Opto-electronic integrated circuit |
| KR930017158A (en) * | 1992-01-14 | 1993-08-30 | 김광호 | Semiconductor package |
| CN113013288A (en) * | 2021-02-05 | 2021-06-22 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
-
1980
- 1980-08-08 JP JP55109943A patent/JPS6027196B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5734375A (en) | 1982-02-24 |
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