JPS6028142B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

In conventional semiconductor devices having silicon wiring, a thick insulating film is formed on a single crystal silicon substrate, and then a polycrystalline silicon layer is formed over the entire surface. Next, polycrystalline silicon wiring paths are formed by chemical etching. The entire exposed surface (top surface and side surfaces) of this silicon wiring is oxidized. However, with this method, chemical etching of relatively thick polycrystalline silicon cannot form fine patterns with high precision in a planar shape.

Furthermore, since the upper surface is also oxidized, the initial layer thickness cannot be maintained.
It is also conceivable that the impurity concentration cannot be maintained at the initial value during the thermal oxidation process. An object of the present invention is to provide a method for manufacturing a semiconductor device having an effective silicon wiring which eliminates such conventional drawbacks.

The features of the present invention include a step of providing a silicon layer on a semiconductor substrate, a step of selectively providing a heat oxidation-resistant pattern on the silicon layer, and a silicon wire having a thermal oxide film coated on the side surface by heat treatment. A method of manufacturing a semiconductor device includes a step of forming a silicon wiring, and a step of introducing an impurity into the silicon wiring.

According to the present invention, the silicon wiring is determined by a relatively thin heat-resistant oxidation pattern, such as a pattern of a silicon nitride film, so that a fine wiring pattern is possible. Further, since the top surface is not oxidized in the thermal oxidation process of the side surfaces, the silicon wiring has a predetermined layer thickness. Furthermore, since impurities are introduced after the thermal oxidation process, the silicon wiring has sufficient gas conductivity. Further, in the present invention, if a part of the thermal oxide film on the side surface is removed, the side portion of the wiring becomes a plurality of steps, so that there is no disconnection in the wiring that crosses over the side portion.

Also, with the silicon wiring of the present invention, is it possible to determine the thickness of the upper insulating film later regardless of the thickness of the side insulating film?Is it possible to reduce the height of the wiring including the upper insulating film? I can,
Therefore, there is no risk of breakage occurring in the wiring that crosses over it.

According to one example of the manufacturing method of the present invention, a thin silicon nitride film (Si3N4) is formed on an insulating layer, a polycrystalline silicon layer is formed thereon, and a silicon nitride film is further formed.

Next, the heat-resistant oxidation-resistant silicon nitride film is selectively removed by an appropriate method, leaving the upper layer of the silicon nitride film in the portion that will become the polycrystalline silicon wiring. Thereafter, using this silicon nitride film as a mask, the polycrystalline silicon is etched to form polycrystalline silicon wiring. Next, this polycrystalline silicon is thermally oxidized to be covered with a silicon nitride film, and only the side surfaces of the polycrystalline silicon layer that are not present are made into insulators. Then, this silicon nitride film is removed and impurities are introduced into the silicon wiring. Also, if necessary, a part of the thermal oxide film on the sides is removed. Next, embodiments of the present invention will be described with reference to the drawings.

In this embodiment, the present invention is applied to a semiconductor device including a P-channel silicon gate field effect transistor element in which a technique related to the present invention is applied to a silicon gate portion. As shown in FIG. 1A, a silicon dioxide insulating layer 2 having a thickness of about 1.0 microns is formed on one main plane of an N-type single crystal silicon substrate 1 with a thickness of about 50 µm by thermal oxidation, and The surface 3 of the substrate 1, which will become the source region, drain region, and gate region, is exposed using a photolithographic mask and etching technique.

Next, as shown in FIG. 1B, a silicon dioxide gate insulating film 4 with a thickness of about 1000 angstroms is grown on the surface 3 of the substrate 1 by a thermal oxidation method, and then a silicon nitride film 5 of about 100 angstroms thick is grown on the entire surface. A polycrystalline silicon layer 6 having a thickness of approximately 4000 angstroms is formed thereon.
After growing, a silicon nitride film 7 having a thickness of 200 to 1000 angstroms is formed over the entire surface.

As shown in FIG. 1C, the silicon nitride film 7 is etched by photolithography to leave the silicon nitride film in the region to become the gate electrode and the region to become the silicon wiring of the present invention.

Using the silicon nitride film in these regions 8 and 9 as a mask, the polycrystalline silicon layer 6 is etched to form a polycrystalline silicon gate electrode 10 and a polycrystalline silicon wiring 1 as shown in FIG. 1D.
1. These polycrystalline layers 10 and 11 are thermally oxidized to form a silicon dioxide insulator 12 that penetrates into the side surfaces of the polycrystalline silicon layers 10 and 11 to about the same thickness as shown in FIG. 1B.

Silicon nitride film 5, silicon nitride films 8 and 9 exposed to the surface as shown in FIG. 1F using silicon dioxide 12 as a mask.
etching. The silicon nitride film 13 under the gate electrode 10 and the insulator 12 and the silicon nitride film 13 under the polycrystalline silicon wiring 11 and the insulator 12 remain. Gate insulating film 4 is removed using silicon nitride film 13 as a mask to expose substrate surface 3. At this time, the surface and side surfaces of the silicon dioxide 12, which is an insulator on the side surfaces of the polycrystalline silicon layer, are etched away to the thickness of the gate insulating film 4, respectively. Therefore, the side surface of the silicon wiring 11 is at a step with the upper surface of the insulating film 12, and the silicon nitride film 13 is below it.
Three steps are formed: the step with , and the step with the silicon dioxide layer 2 below, forming a gradual multi-step shape with rounded corners. Poron is diffused into the substrate surface 3 to a depth of about 1 micron to form a source region 14 and a drain region 15. At this time, boron is also diffused into the polycrystalline silicon 10 and 11 to make them conductive. Next, as shown in Figure 1, the entire surface is covered with an insulator, and the insulators on the source region 14, gate region 10, drain region 15, and polycrystalline silicon wiring 11 are each etched by standard photolithography. Hole 16, 17, 1
8 and 19 are formed, and the aluminum wiring 20 reaching these openings is closed. It is also possible to further improve the conductivity of the polycrystalline silicon wiring by diffusing impurities before forming the silicon nitride film 7 on the polycrystalline silicon 6 in the process shown in FIG. 1B of the above embodiment.

Furthermore, when etching the gate insulator 4 in the process shown in FIG. It is also possible to prevent the aluminum wiring from becoming thinner by dividing it into equal parts. Although the present invention was applied to a silicon gate field effect transistor in the above embodiment, it is also applicable to general semiconductor devices.

For example, a semiconductor material such as germanium or gallium can be used instead of single crystal silicon. Further, as the insulating film, silicon dioxide or the like formed by thermal oxidation, vapor phase growth, vapor deposition, sputtering, etc. can also be used.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional model diagram showing the manufacturing process of a silicon gate field effect transistor to which the present invention is applied. 1... N-type single crystal silicon substrate, 2...
・Silicon dioxide insulating film, 4... Silicon dioxide gate insulating film, 5... Silicon nitride film, 6...
...Polycrystalline silicon layer, 10...Polycrystalline silicon gate electrode, I1...Polycrystalline silicon wiring, 1
2...Silicon dioxide insulator, 14...
・Source region, 15...Drain region, 20.
...Aluminum wiring.

Claims (1)

[Claims] 1. A step of providing a silicon layer on a semiconductor substrate, a step of selectively providing a heat oxidation resistant pattern on the silicon layer, a step of etching the silicon layer using the heat oxidation resistant pattern as a mask, and heat treatment. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a silicon wiring whose side surface is coated with a thermal oxide film; and introducing an impurity into the silicon wiring.