JPS6028383B2 - Selective impurity diffusion method into semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for selectively diffusing impurities into a semiconductor substrate, and particularly to an improvement in a method for selectively diffusing impurities into a semiconductor substrate.
This is suitable for application when obtaining an S-type field effect transistor.

Hereinafter, the present invention will be described as being applied to the case of obtaining an S-type field effect transistor (hereinafter referred to as MIS-type FET for simplicity). An insulating thin film 2 made of, for example, a silicon oxide film is selectively applied on a semiconductor substrate 1 (FIG. 1A) (FIG. 1B), and then a region on the semiconductor substrate 1 including the top of this thin film 2 is coated. A polycrystalline semiconductor layer 3 made of, for example, polycrystalline silicon containing an N-type impurity is formed (FIG. 1C), and then heat treatment is performed to remove the particles contained in the polycrystalline semiconductor layer 3 from areas other than on the thin film 2. The impurities are diffused into the semiconductor substrate 1 to form impurity diffusion layers 4 and 5 (FIG. 1D).
After that, the polycrystalline semiconductor layer 3 is removed except for the region 6 on the thin film 2 by a photolithography process (FIG. 1E), and then the region 6, impurity diffusion layers 4 and 5 are removed. A MIS type FET including a step (not shown) of forming a wiring layer that can be extended further to obtain a MIS type FET in which impurity diffusion layers 4 and 5 are used as sources and drains, thin film 2 is used as a gate insulating layer, and region 6 is used as a gate electrode. FET manufacturing methods are currently in use.

However, when such a manufacturing method is used, the photolithography process described above is required to obtain the region 6 that will become the gate electrode, which makes the entire process complicated, and the formation of the wiring layer is difficult. However, since the region 6 is formed in an uneven state in which it protrudes from the upper surface of the substrate 1, it has the disadvantage that it is difficult to obtain a fine wiring layer.

Therefore, the present invention can effectively avoid the above-mentioned drawbacks when applied to the case of obtaining a MIS type FET including the step of diffusing impurities into a semiconductor substrate as described above.
The present invention is intended to provide a novel method for diffusing impurities into a semiconductor substrate, and the following will become clear from the description of an example in which the present invention is applied to obtain an S-type FET, as shown in Figures 2 and below. o As shown in FIG. 2, a P-type semiconductor substrate 11 (FIG. 2A) made of silicon, for example, is prepared in advance.
), an insulating thin film 12 made of a silicon oxide film is formed over the entire area by, for example, thermal oxidation treatment on the semiconductor substrate 11 (FIG. 2B), and then on this thin film 12, an insulating thin film 12 is formed over the entire area. A polycrystalline semiconductor layer 13 made of polycrystalline silicon containing an N-type impurity, such as phosphorus, is formed by, for example, vapor phase growth (FIG. 2C), and then, on this polycrystalline semiconductor layer 13, a film is deposited over the entire area. Then, a layer 14 made of, for example, a silicon nitride film is applied by, for example, a vapor phase growth method (see FIG. 2D).
), then, for example by photolithographic techniques, layer 1
The required regions 15 of No. 4 are left as an oxidation inhibiting layer and the other regions are removed (FIG. 2E).

Next, a region 16 of the polycrystalline semiconductor layer 13 under the oxidation inhibiting layer 15 is subjected to thermal oxidation treatment on the polycrystalline semiconductor layer 13 by performing heat treatment in an oxidizing atmosphere such as moist oxygen.
Thin film 1 removes impurities contained in that region from other regions.
2 into the semiconductor substrate 11 to form impurity diffusion layers 17 and 18 in the semiconductor substrate 11, and at the same time fill the entire thickness of the regions 19 and 20 of the polycrystalline semiconductor layer 13 other than the region 16. It is then oxidized to form insulating regions 21 and 22 which extend to region 16 and exist on thin film 12 together with region 16 (FIG. 2F). The mechanism by which the impurity diffusions 17 and 18 and the insulating regions 21 and 22 are formed by this step is as follows.

That is, the impurity concentration distribution of impurities contained in the region 16, the thin film 12, and the region 16 of the semiconductor substrate 11 as seen on the W-X line extending in the vertical direction passing through the region 16 is as shown in FIG. 3A before thermal oxidation treatment. As shown, although the region 16 exhibits a uniformly large impurity concentration over the entire region along the W-x line, the thin film 1
2 and the semiconductor substrate 11 have an impurity concentration distribution in which the impurity concentration is uniformly zero over the entire area along the W-x line, but under such conditions, the thermal oxidation treatment is carried out for the scheduled time. For example, if impurities contained in the region 16 enter the thin film 12 from the region 16 side, the impurities will pass through the thin film 12 to the substrate 12 because the region 16 is not oxidized.
Therefore, as shown in FIG. 3C, after passing through the impurity concentration distribution shown in FIG. It is intended to be presented. However, the impurity concentration distribution in the regions 19 and 20, the thin film 12, and the substrate 11 as seen on the Y-Z line extending vertically through the regions 19 and 20 is as shown in FIG. 4 before the thermal oxidation treatment. As shown in FIG. 3A, regions 19 and 20 exhibit a uniformly large impurity concentration over the entire area along the Y-Z line, but the thin film 12 and the substrate 11 are Although the impurity concentration distribution is such that the impurity concentration is uniformly zero in the entire area along the line, if the thermal oxidation treatment is carried out for the scheduled time, regions 19 and 20' will be included. impurities entering the thin film 12 from the regions 19 and 20, but the regions 19 and 20 are
The impurity concentration on the thin film 12 side of regions 19 and 20 increases with time due to the polarization of impurities at the interface between the oxidized region and the non-oxidized region. If all of the regions 19 and 20 are oxidized, the impurity concentration at the interface between the regions 19 and 20 and the thin film 12 will increase rapidly, and therefore the impurities contained in the regions 19 and 201 will easily enter the thin film 12. As a result, the impurity concentration of the thin film 12 increases, and the thin film 12 and the substrate 11
Coupled with the polarization of impurities at the interface between Through the impurity concentration distribution shown in B, regions 19 and 20 exhibit impurity concentrations that are significantly lower than those before the thermal oxidation treatment, and the thin film 12 exhibits a large impurity concentration on the regions 19 and 20 side. , the impurity concentration distribution is such that the substrate 11 has a large impurity concentration toward the thin film 12 side. In this way, impurity diffusion layers 17 and 18 having an impurity concentration distribution as shown in FIG. 4C are formed in the substrate 11, and the regions 19 and 20 are oxidized to have an impurity concentration distribution as shown in FIG. In this case, the oxidized regions 21 and 22 are formed. In the above manner, the impurity diffusion layer 17 is formed in the substrate 11.
and 18 are formed, and a region 19 of the polycrystalline semiconductor layer 13 is formed.
and 20 are formed as insulating regions 21 and 22. Next, the oxidation inhibiting layer 15 on the regions 16 is removed, for example, by an etching process (FIG. 2G), and then, for example, the insulating regions 21 and 22, and a rear region 16 by forming windows (not shown) in the thin film 12 for the impurity diffusion layers 17 and 18;
A wiring layer extending from the impurity diffusion layers 17 and 18 is formed (not shown), so that the impurity diffusion layers 17 and 18 serve as a source and a drain, respectively, the region 16 serves as a gate electrode, and the thin film 12
Skin S type F in which the region 23 below the region 16 is the gate insulating film.
Get ET.

The above is an example of a method for manufacturing a MIS type FET when the present invention is applied to obtain a skin S type FET. Unlike the conventional case described above, a photolithography process is not required, and although a photolithography process is required to obtain the oxidation inhibiting layer 15, the thin film 12 that will become the gate insulating layer is formed as shown in FIG. Since there is no need to selectively obtain a thin film as in the case of a secondary structure (in which case a photolithography process is required), the desired MIS type FET can be obtained through a simple process overall. It is possible.

In addition, a region 16 that becomes a gate electrode and insulating regions 21 and 22
are connected to each other and extend uniformly over the thin film 12, making it much easier to form a wiring layer than in the case described above with reference to FIG. Therefore, it has great features such as being able to form a large number of MIS type FETs in a highly concentrated manner. As described above, the present invention is extremely suitable for application to the case where a MIS type FET is obtained by including a step of diffusing impurities into a semiconductor substrate.

In the above description, the present invention was applied to the case of obtaining a MIS type FET including the step of diffusing impurities into a semiconductor substrate, but it is also possible to apply the present invention to the case where the opposite or the same conductivity type is imparted to the semiconductor substrate. It will be obvious that the present invention can also be applied to the case where a desired semiconductor device is obtained by including a step of diffusing impurities.

[Brief explanation of drawings]

Fig. 1 is a schematic cross-sectional view of each step in obtaining a conventional skin S-type FET, and Fig. 2 is a MIS-type FET obtained by applying the selective impurity diffusion method into a semiconductor substrate according to the present invention. 3A to 4C and 4A to 4C are diagrams showing impurity concentration distributions for explaining the process. In the figure, 1 and 11 are semiconductor substrates, 2 and 12 are thin films, 3 and 13 are polycrystalline semiconductor layers, 4, 5, 17 and 18 are impurity diffusion layers, 6, 16, 19 and 20 are regions, 14 is a layer,
Reference numeral 15 indicates an oxidation inhibiting layer, and 21 and 22 indicate insulating regions, respectively. Figure 1 Figure 2 Key figure 3 *4 Figure

Claims (1)

[Claims] 1. Forming a polycrystalline semiconductor layer containing impurities on a semiconductor substrate via a thin film, selectively applying an oxidation inhibiting layer on the polycrystalline semiconductor layer, and then performing an oxidation treatment on the polycrystalline semiconductor layer. By this, impurities contained in the polycrystalline semiconductor layer from a region other than under the oxidation inhibiting layer are diffused into the semiconductor substrate through the thin film. selective impurity diffusion method.