JPS603025A - Microprogram control system - Google Patents

Abstract

PURPOSE:To reduce the bit-directional capacity of a control memory and improve ecomony by providing plural readout registers of the control memory, using them properly through a control means, and using the starting address of the control memory selectively. CONSTITUTION:The 1st control memory 2 is stored with mircoinstructions to be executed by a data processor, and those microinstructions are read out to a microinstruction register 3 and executed. The 2nd control memory 11 is stored with a specific field indicating the starting address of the routine of the microinstructions stored in the 1st control memory 11. For the purpose, readout registers 12 and 16 for the 2nd control memory 11 are provided and used properly to input the starting address of the 2nd control memory 11 to an address circuit 13 selectively.

Description

[Detailed Description of the Invention] The present invention provides a data processing device that provides +? This invention relates to an improved microprogram control method for controlling addresses for control memory.

[Prior art]

Conventionally, in the microprogram control force formula.

To control the address 74 to control memory.

Method for decoding the operation code of the instruction register and accessing the control memory-': ・Place a second control 11 memory between the instruction register and the control memory, and store the instruction h in it.
A method has been adopted in which the first address of the control 1 memory is allocated for every 1+, and the second control memory is accessed by the operation code of the instruction word t'1. According to this method, the start address of the instruction word in the control memory is read from the corresponding address block 1-7, the control memory is accessed, and the data is processed by executing the issued microinstruction. The equipment rA was controlled. However, in these methods.

Since the starting address was different for each macro instruction, a large amount of control memory was required. + as a method to improve fear! The ti control memory is divided into a boot preparation routine table execution routine, the Mac0 instruction can be used commonly for each routine block in the control memory, and the start address of each routine is stored in the second control memory. 3. In this method, multiple addresses stored in the second control memory are stored in one word for each macro instruction. The second
The capacity in the bit direction of the control memory is changed by adding 1%. Therefore, no matter which method is used in -1-, /・-
This will lead to an increase in the number of douware, which is not economical.

[Purpose of the invention]

The object of the present invention is to: When accessing the second control memory,
Multiple registers for performing necessary control and how to use these registers interchangeably? Ii control means is provided, and when a macro instruction is executed, l, λ are first read out from the second control memory;
7fr and 2nd according to the state of f control frinno ° frog
By not reading the memory, the second fti
A microsologram in a data processing device that can store a microprogram without reducing the number of control memory (Pino) and directions, and without increasing the first control memory trough: 11-. The objective is to provide a control method.

All days below 1. Structure of the invention] The microzologram control method according to the present invention is as follows.

It has an instruction register for holding an instruction iin, and a first control memory for storing a microprogram, which is read out from the first control memory according to a macro instruction from the instruction register and processed by the microprogram. In a data processing device that performs.

The microinstructions read from the first control memory are held 1-. A) A) of the microinstruction register to be executed and the microinstruction to be executed 9th.7. and the first one! l
a second control memory storing a specific field indicating a start address of the microinstruction routine stored in the first control memory; A plurality of registers alternately hold specific fields read from the second control memory in response to an update instruction signal of the instruction register; a second address means for supplying an address determined by the f't code and an instruction register update instruction signal; at least a particular field of said second control memory; and said 4', ! Before holding the i constant value N
yv nosta, and means for controlling the first and second address means in response to one microinstruction in the first control memory. It is characterized by

[Embodiments of the invention]

Next, an embodiment of the micro-log sim feed control system according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the configuration of a boot processing device as an embodiment to which the present invention is applied. This I
In gl, 1 is the command reno nuta, 21d J's f!
III control memory, 3 is microinstruction register.

4 is an address register for the first control memory, 5 is a +1 adder, 11 is a second control 11 memory, 12 and 16 are read registers that hold specific fields of the second control memory, and J3 is a first address. circuit (adreno means),
14 is a control circuit (control means);

+5fd is a second address circuit (address means).

The first system (j) 7 normally decodes the macro instruction to be executed by the data processing device and executes the micro instruction that is LlL to the macro instruction. When a macro instruction is executed, the first control memory address 1jrl start address is 1jrl in the address nosk 4.
Through 3.1-I) can be obtained. And this starting al
The reinforcement device 5-\ is passed through the lines 401 to 403.
Sent to read an address. This signal is energized and sent to the first address circuit 13 through the address line 501. At this time, the address which received -1 in the first address circuit 13 has a signal rate 'rJ 50.1
Is it an address from f (by +1 power 0 wisdom, heat:・)5?

i1: issue i! 11121, the start address sent through the signal line 161, or the signal line +1. Controls whether the start address is sent from II through 113 @141゜142
．． The selection is made by signal control from 143 and 144. The address from the +1 adder 5 is selected] 1<The first address circuit is selected as described above] from 3.
-Bi'AdditionalTL7'AdjustmentA [゛Renu or first control ir[I
It was sent to I Memoria l + Wrestle Nosta 4, and as a result, Shin Yutada! 40]> and accessing the tenth control 1 memory 2 through 402 1, by this 1.

First restriction] From the memory 2 through the signal line 201, the micro-instruction in the address location (+(note 1.
f-:sanoin:' 61. In! ', i*'; eye, booster; obtained by 5/(-to address', Rijino Z
Then, the microinstruction I or the microinstruction renostar 3K#1'' is output from the first storage 11 memory 2, and the main command (J command) is executed.

By the way, when a macro instruction is executed like this,
The Yukizu instruction Reno Nuta 1 (/ko macro instruction) is extracted from the main memory (not shown) and held. The contents of the instruction recorder 1 are updated in response to the recorder history update 100. When the instruction recorder 1 is updated, the contents of the control circuit 14 are updated. In FIG. 2, the control 1 controller 14-1 receives the same update signal 100 and is set to ``2''. 1'' appears in the least significant bit of . Then, the instruction renoster 1 is updated, and as a result, the updated operation code of the instruction renoster 1 is sent to the second address circuit 15 through the signal line 101. second ato 17
The output of the circuit 15 accesses the second control memory 11 through a signal line 151. Second control memory] Contents of specific tool 1 (start address) read from 1/ζ
+d iriq % line 111 to j city and read register 16
．． Katsutake, Shiride Renostar 12t/ko set. Here, which one is set depends on the contents of the control circuits 14-1 and 14-2 of the control circuit 140.

I1. In FIG. 2, control 1 Frizzo Fronno',
+4-] is 1'', the control frizzoff.

If 14-2 is "o", signal line], 40
1.

The contents of the control frizzoff' 1.4-1 are sent to one input of the AND circuit 14-8 through 1402 and 1403, and further signal lines ], 407, i 41
1 to the other input of the ANI) circuit 14-8 is sent the contents of the control fluff 014-2. At this time, the AND circuit 14-8 is the output signal line! Output logic Ll i II to 1406 and control flip knob 14-
" ] " is set in 2. As a result, the respective 6611 signal values appear on the output signal line 146 of the AND circuit 14-4 and the output signal line 145 of the AND circuit 14-5. That is, the AND circuit 14-4 has a signal line of 1.40].

] 402, the logic "1" through 14.04 is -
Logic "1" is input to the other power through the signal line ]/107, 1.408, resulting in an output signal of 1%
! "]" is output to 146. ANI) circuit] 4-5.

1" is sent to one input through the signal lines 1401, ] 402, ] 405, and the signal -5 is sent to the other input.
Part 1] “0” is reset through 407°1409.

As a result, the 7 output signal line 145 becomes logic 1°Oll.

As described above, the start address read from the second control memory 11 is sent to the readout reno star 2 by the outputs energized to the signal lines 145 and 146, and the signal Vi! ]
] ] , 1 ] Set through 2.

It is not set in the read reno star 16. In the state of 1. Output signal Y3 line 20 of the first control memory 2 being accessed by the control memory address inputter 4
2, if there is a microinstruction indicating the last microinstruction stelaph 0 of the macroinstruction in the actual instruction "J", the control circuit 14 will respond twice by this output No. 1. microinstruction in response to a microinstruction indicating steer 0.

According to the operation code of the instruction word held in the instruction code 1, the second ! till
l&iil memory 11 is accessed. Namely.

The /ξlli force obtained on the signal line 202 is transferred to the decoding circuit +4 as shown in FIG. -, I OK given and decoded, French-bow line +412. +413 through 匍j
0707ノ' ], 4. -1 is reset. As a result, the signal line 1 is connected to the second address circuit 15.
47, the least significant bit "0" is sent, and at the same time, the operation code sent via the signal line 101 accesses the second production 11 memory 11. The start address read from the second control memory 11 is also .

The first address circuit 13 through the signal line Ill, 113
It is JXed by. Here, the content from the signal line 113 is selected by the signal line (141) and sent to the first control output 4 through the bow lines 1 and 31, and then the first control file Access memory 2. After that, when a microinstruction instructing the switching of the start address appears on the signal i1202, the decoding circuit 14-10t generates the signal &! +4] 8, 14] 9° 1420 is the 9th dimension where the selection signal is sent, control flow, flow, inner line of F'14-2, A17 bow, 1 line 14I2 becomes "]" When the input signal line 414 of the AND circuit 14-9 also becomes "1", the 1.3 line 1407, , +4
Output number 11 of AND circuit 14-9 through 10, i''
! Output j゛' to j I 415. Thus, the control f
+11 Nori, no 0 frog 14-3 is set. When there is an instruction to switch the start address, the control goes from the output side of ZONROTSUNO'+4-3 to the AND circuit 14-6 manually (/("V").

The input of AND circuit 14-7 is 0'' or 1-1+, respectively.
Ji Mi! J, 4] 6, 1417 because it is strengthened through.

The output signal line 144 of the AND circuit 14-6 is connected to the output signal line 144.

The output signal line 1.43 of the sum circuit 14-7 is connected to either P0''' or 7.
-7 can be obtained. As a result, in the first address circuit 13, the contents of the read register 12 are selected through the signal line 121 by the signal line 144, and sent to the first control memory address register 4 through the signal line 131.

Next, in FIG. 2, when the instruction register 10 update signal appears on the signal line 100, the control knob flop 14--
Since 2 is held at I+1 gH, the AND circuit is turned on at the primary timing. As a result, the signal lines 1407°14.08, 14
(Signals are sent to AND circuits 14-4 and 14-5 through 19, but since these signals are '0''', the output signal line of AND circuit 14-5], 45, K
"]," is sent. As a result, the second address circuit 1
5 has "]" in the least significant bit as mentioned above,
The second control memory 1] is accessed. Then, the execution start address of the seventh macro instruction is read out, and the signal line 11
5 to the read register 16. Control flip-flop 14-1 is activated after 1'' appears on signal line 100.

When a ficro-instruction indicating the last micro-instruction step of the macro-instructions appears on the output signal 202 of the first control memory 2, +f=r-to circuit J4-. 1. The signal is block-coated from OK, and the signal line 14J2 and signal line 14 are
1 becomes 1"'. This causes the control frill rough 0
Tsufu oI 4-1 beam is set. pretend.

When the flop 14-1 is set to 1, the operation code of the instruction register 1 and the output of the signal line 147 become 0'', and the second address circuit j5 does not read the start address of the next macro instruction. The second control memory 11 is accessed through the signal line 151.
1,113; 1T+ and the read contents are sent to the first address circuit 13. The first address circuit 13 selects the output of the signal line 113 through the signal lines 4 and 4 and sets it to the first memory address 4 through the M line 113.Control circuit 1
A1 in 4; @ line 142 is set and the +1 address of the /ζ address is sent to the first address W? J1
It will be used in the 7th time selected in step 3. After that, the start address switching instruction is sent to the output signal line 2 of the first control memory 2 again.
02, the read register 12. Either the read register 16 or the read register 16 is selected. by the way,
Control flop J4-2 is set to °'0''', 1.
Since signal line 1,412.1414 is 1″'
7, 0'' appears in the output of the AND circuit 14-9 from the contents of the output signal line 14o7 of the Furi Ruff 0 Frotzf'14-2, and ?ft1l ml Flinlennorotsuno014-3 becomes 0''. Set. Then, AND
The output signal line 143 of the circuits 14 to 7 becomes l''.

AND lj'jl path 1.4-6 (D output signal line 144
becomes II OII. Thus, in the first address circuit 13, the contents of the read register 16 are selected by the signal line 143 through the signal line 161, and are set to the first control m+ memory address register 4 through the signal line 131.

will be played. In this way, seven macro instructions are executed one after another by alternately using the read register 12 and the read register 16 for the start address.

[Effects of the Invention] As is clear from the above description, according to the present invention, a plurality of registers for reading the second flt control memory are generally provided, and these registers are selectively used by the flt control means. By selectively using the starting memory of the second control memory, the bit-wise capacity of the second production 11 memory can be reduced.

The effect of improving hardware economy is significant in that it can be implemented without increasing the micronogram of the first control memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a 1η configuration, and 2121 is a block diagram showing a specific configuration example of the control circuit in FIG. 1 according to an embodiment of the present invention.
1 is an instruction memory, and 2 is a first control memory. 3 is a microinstruction register, 4 is an address register,
5 is +1 + 81: vessel, 11 is the second 17 + 1 star memory. ], 2, 16 is a read register, 13-digit first address circuit, 14 is a control circuit, 15 is a second address circuit,
14-1-3 is control frisogunroson', 14-4 to 9
is an AND circuit, and 14-10 is a code circuit. Figure 1

Claims (1)

[Claims] 1. An instruction register that holds an instruction word and a first control memory that stores a microprogram, and that is read from the first control memory in accordance with a macro instruction from the instruction register. Micro. In a data processing device that performs processing using a program,
A microinstruction register holds a microinstruction read from the first control memory and an address of a microinstruction to be executed first. a control memory address register for supplying to the first control memory; and a second control memory storing a specific field indicating a start address of a microinstruction routine stored in the first control memory. and a plurality of registers that alternately hold specific fields read from the second control memory in response to the instruction register update instruction signal. a second address means for f-copolymerizing an address determined by an operation code of the instruction register and an update instruction 'fM of the instruction register in order to read the second control memory; Select the output of the register in the rear register that holds the specific field, and select the output of the register that holds the specific field, and select the output of the register that holds the specific field. a first address means for supplying an address to a till g41 memory address register; and said first control memory responsive to one microinstruction V;
A micro-70 program control method 1, characterized in that it is constituted by a means for controlling the 71-renu means of the first notation 2.