JPS603034A - Time monitoring circuit - Google Patents

Abstract

PURPOSE:To constitute numbers of timer circuits which have high precision and a wide settable range at low cost by using a timer control circuit in common. CONSTITUTION:A timer registration register part 1, timer control word storage part 3, and registration address pointer part 4 hold a timer control part, plural control words, and the address of a timer control word storage part for timer registration respectively. An internal interval timer part 5 has three kinds of reference value timer circuits specified by the reference timer value filed of a timer control word. An updating address pointer part 6 holds the address of the timer control word storage part for timer updating. A timer updating register 7 holds the readout output of the timer control word storage part 3 during timer updating and has a decrementer in its monitor time value field. The contents of the registration address pointer part 4 and updating address pointer part 6 are compared with each other by a comparator 8, whose output is supplied to the registration updating control part 2 of a timer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-programmable time monitoring circuit.

As a time monitoring (hereinafter, "11 1η!! iii" will be abbreviated as "-timer") circuit, there is one fixed path. It was realized by a Pinaritsu J counter, each composed of Frisof flops1, so if it was necessary to implement it with multiple timer circuits in hardware, it had the disadvantage of requiring a huge amount of hardware1. In conventional timer circuits, the update interval of the valley counter depends on an external reference clock (constant clock). It was necessary to add 1.!7 to the number of bits.

<Overview of the invention> This invention solves the drawbacks of
By standardizing the J control circuit and making it possible to allocate timer counters in a timely manner, increasing the number of timer circuits that can be set per J with a small amount of hardware, and by setting a reference timer value when a timer is requested, the number of counter bits can be reduced. 1. Embodiment FIG. 1 shows a timer circuit that is used in an embodiment of the present invention and is output from an external circuit. This is an example of the format of the 17j control word (T may be written as 4CW), and the 8-hit 'rrn61 time value field of the 0th to 7th bits, 8. 74 +, -4 of 9-bit 2-pin), -4 = timer 1 direct field, 1st (J, fi;, , 1] timer type field of 2 hits), 12th to 4 of 5th hits Hit's path ft'r->'r group identifier field and 8-hit pass number of 16th to 23rd bits>3-field is growl i'jl RI2 holiday time 1 shift field V'1, O~255 If you multiply the setting value by the standard timer value described below, you can set the required monitoring time of 1l.
It will be between JJ. In the reference timer value field, 10 milliseconds, 1 second, and 1 minute can be specified as reference timer values. For example, if you specify "milliseconds" in the standard timer value field, the time from 0 to 2560 milliseconds will be set to 0 if you specify 1 minute.
~256 minutes of time Xunso Jl each 9trj: It becomes possible to give instructions. Previous + jL timer (Nakabetsu field wa", L" O
~T 3 J-ji box is created, 171J-1', 'l line 4
．． ,, ()# Different timers can be set for i dimension. 1
) [The bus number group identifier fivert indicates a timer request method, and can be made to correspond to a processing routine in the communication control program, for example)11).

r? If the path number field indicates the timer (i-indicates the line number to request), Figure 82 shows a block diagram of the 71i!11-11 of this invention. Timer registration register B1112 (d timer registration update system side 1 part, 3 is a timer control word storage unit that holds a plurality of timer ilj control words, 4 (d) is a timer registration register for timer flillIi11 nfa storage unit address It is a registered address pointer section that holds , and has an incrementer/decrementer. 5 is the base of the timer fti control word (■ internal interval timer analysis with three types of criteria 11 to timer l1jj specified in the timer 1 direction field, 6tl: 1 timer history gj JTJ Holds the timer control word storage unit address (new address pointer unit, has an incrementer.

7 is the number of timer circuits when updating the timer.
t; -3: This is a timer update register that holds the F7C output, and the monitoring time 11r1- field has a techrementor. Comparing the fields, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, and 1, respectively, are shown. The control is operating within part 1 and 2. Timer '11i control KM part 1.6; 37)
・Check the time mask overflow flag, which indicates an automatic flow.
If so, increment the registered address pointer section 4.
Control the timer using the (+], ) value as the address.
Mf' is registered in the storage unit 3. Timer control 1 of the register unit 1;
Osamu (to pay)

Note that if an overflow occurs as a result of incrementing the registered address pointer Fil; 4, that is, if the timer control word memory 81S3 indicates that /i:'jr is full, the <) record address pointer section 4 is updated, and 4" to the timer control word storage unit 3. [Do not perform one payment, set the timer mask overflow flag to "i," and set the timer mask overflow flag to "i," and generate a flow interrupt. The timer control M that automatically flowed
1 from the timer registration register 1.

When a timeout occurs from one of the internal interval timers H-4B5, the registration update control unit 2 uses the contents of the update address pointer unit 6 as an address to update timer 1.
liili: rFFki: '11'! , From part 3, I bottled the timer IF IFI, and the timer history Yj1 / Stuff f-stupid 1-! , Do 5, (Insufficiently;i;:lI included, or specify in the timer type field in the timer control word of lj i-%f4 timer sep→j1 and history oj1/staff. The difference between the timer type and the match difference is
[The timer control ff4. '+i: Increments the inner part of the i visual time field. 1) of that chikliment? , If you are stunned or become "CI"Q" 2. Interrupt the external circuit with the occurrence of tights and outs 1.
The timer control word that has timed out can be recovered from the timer history 1 bulldisk 7. Said・1:1°j1cedar 1111゛J]11]111
'If the result of ticking of the J field is not "(1"), the timer system f1 mark iij 0 is set to 1 address pointer jrlj 6 of 7''ζ.
If the timer 1 does not match, the response pointer 6 is incremented and the next timer 1lr1. l 1ilil i:! j
The process moves to the history YIi process.

By updating the timer control trt, the timer: 1ill
If you cut 1, 'ljj, 1 tally, T'M CW (2 + (
(Fig. 3), when a timeout occurs, the corresponding timer input φ'1 word is sent to the timer jlill_111r: rni1.
δi'? H3 yen cut E'Jb, timer! ! i
lI Conquest 1 Edict゛; 50 parts 3 no. 1 + li L-no'1
・[/su history su t a I- reply pointer vice s From rule 61, 0 meeting 1. , +)' Tresboi/Li HlB 4 Switch to i-law and tie-7111sfi11 of (11)
1 word memory - 7X153 contents, J) ichi timer: 1il
1 phrase If , ii'i 'L' l list 'ICW (, j+
1), and after storing it in the timer update register 7, register +:, l, address blank section 4.
8 of them from lI"E to Ii"D, timer control 11i1 a! ,! The read address of the storage section 3 is moved to the history 1 file 1 address pointer section 6], and the update processing of the timer control word i,' ]VICW (j + 1) in the timer update register 7 is transferred to the contents 02 of the blank section 6. 1゛1\II CW (j+1
) into address 02 by 〒1. Figure 3: TM CW
(j-1-1) is the latest timer'lti control word, and "□" indicates the by:vif poison range.

The update address pointer section 6 is sequentially incremented to update the timer control 1 word, and the timer control 1 word of the address where the contents of the update address pointer section 6 and the registered address pointer section 4 match in the comparator 8 is updated. When the above-mentioned one reference timer is updated by interrupt,
41! ends.

When the timer master overflow flag is “1”,
Timer update processing - 118111 If a certain amount of empty space is generated in the evening/f timer system tll iA storage unit 3 due to the 1-out processing, the registration update system y++4 is set to 2d-timer stack overflow flag. When I set it to 0'', an interrupt of 7'' was generated in the first circuit, which caused an interrupt equal to 1 in the timer stack Oats-Solow. It is possible to output Satoru., timer stack overflow release egg "incl./(11') of empty area of C", id:
, timer history due to timer interrupts to the oppressive 1° group is desirable so that interrupts for timer mask quota flow and release interrupts do not occur in 9 groups.
When Wt Tanchu receives a timer control word from the external circuit, the registration update control unit 2 holds the relevant timer fi:I word in the timer, holds it in the register unit 1, and transfers it to the third timer j.
The update process of l+', l 1i111 +il F is completed, and the timer-controlled decoy l of No. j+1 1-1, i? The update process is interrupted immediately before proceeding to the update process of ;, and the pending timer control word registration process J! 1. Performing 11. <Effect> As explained above, the effect of
Since a flexible timer circuit with a wide settable range can be provided at low cost, the processing capacity of the device can be increased by 11yj, and the cost performance can be increased by 49 digits.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of one form of rl used in this invention; Fig. 2 is a block diagram showing one embodiment of this invention; Fig. 3 is a timer control cape; Is t↑ a timeout? ijl irl'll r
l:Record 1. This is a 1ift transfer of the contents of the lower part and a) record, update address blank part. 1: 772 copies registered with timer, 2: New registration history system; v11)
1≦, 3: Kuimaro Kawayogendairoki 1 neglect 1.4: Registered address pointer 7'11S15: Internal interval timer section, 6: Update atres register section, 7: Timer update register, 8: Comparator. 111 people for patents 11 Honko: 1 and Ichiwa Kosha representative j no 11
Person Taku Kusano 1 Figure 3

Claims (1)

[Scope of Claims] (1, 1, 1+!-BeC-Timer value, timer type, monitoring time value, path H5, >y and O, group ijiπ-discriminator to which the bus number belongs) a timer registration register section for holding the edict; a timer:li control word storage section for storing a plurality of the timer control words; and an address for storing the timer control word in the timer control 1i111 word storage section. a registered address pointer section that maintains the
Read the timer word to be updated from the timer control j word storage section t Update address pointer section that holds the It-th address, timer i]+lI At the time 4rJ of the reference timer value which is 74e with 11 words , the internal interval 4th block 9tS which generates an interrupt signal, and the timer flail 11 words are output from the external circuit Do/Valley, the timer:b! I Talil edict, 08 above.
The timer indicated by the address with 1 added to the contents of the address pointer section? The hand stored in the 1ill steel 1 word storage section and the interrupt kj' from the internal ink-pal timer section
->j-, 1) It is addressed by the 11th column address pointer section, and the timer 1'1j oil 1 is
i+7! #已1. The interval timer that generated the reference timer 1 [σ or not, timer 4 [[, and 'l It') j Δ Noah) -] Applicable timer only if YES/C! ii
: Is it the result of subtracting the 1'tJ- value from the 111th time of the 1st term of the I-1 word?] or - [- is the subtracted IM
-I set the relevant timer word containing the time value to the original r\seal 1'1 in the timer system (di' 1tti memory section, and the previous h12 calculation result is 0;fur; ,,this,≠
The timer of timer 11 and 1t1) is connected to the external circuit.
The means to know and the ;jl:! After learning, the address pointer part of the above 7th record or the small timer control word is issued by MC and the registered address voice is decreased by 1? At the same time as A-, the timer jlJll (t"111ifj history eyebrow processing is performed, and then the update address boiling fr, 11
K.J.Z said timer 1111 ``1, 0, B]
3, and the contents of the updated address pointer section are the same as the contents of the updated address pointer section. 1f, l):Iiil,:Timer control Tsukuda11i1
1 j'j, 41 parts (iii) time monitoring circuit.
A flag is set to indicate that the timer is full, and if it is indicating that the timer is full, the external circuit is sent to the external circuit. ', notifies the occurrence of an overflow in the t1 part, and then executes another process to store a certain number of words in the timer control word storage unit.
If the second empty area occurs, what is the frac a1? Showing lf'1 cup! 1. Notify the external circuit that the overflow is divided by 1 and reset the flag]-
Update the registration i! jf control section is set to 14 characters ((range of x tolerance time stated in item 1! ir:i
', Celebration Circuit,.